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The TPS799L family of low-dropout (LDO), low-power linear regulators offers excellent ac performance with very low ground current. High power-supply rejection ratio (PSRR), low noise, fast start-up, and excellent line and load transient response are provided while consuming a very low 40-μA (typical) ground current.
The TPS799Lxx is stable with ceramic capacitors and uses an advanced BiCMOS fabrication process to yield a dropout voltage of typically 100 mV at a
200-mA output. The TPS799L uses a precision voltage reference and feedback loop to achieve an overall accuracy of 2% over all load, line, process, and temperature variations. The TPS799L features inrush current protection when the EN toggle is used to start the device, immediately clamping the current.
All devices are fully specified over the temperature range of TJ = –40°C to 125°C, and offered in a low-profile, die-sized ball grid array (DSBGA) package, ideal for wireless handsets and WLAN cards.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS799Lxx | DSBGA (5) | 1.57 mm × 1.20 mm |
Changes from A Revision (July 2012) to B Revision
Changes from * Revision (April 2012) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | A1 | I | Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. |
GND | B2 | — | Ground |
IN | C3 | I | Input supply |
NR | A3 | — | Noise reduction; connecting this pin to an external capacitor bypasses noise generated by the internal band gap. This capacitor allows output noise to be reduced to very low levels. |
OUT | C1 | O | Output of the regulator. To assure stability, a small ceramic capacitor (total typical capacitance ≥ 2.0 μF) is required from this pin to ground. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage(2) | IN | –0.3 | 7.0 | V |
EN | –0.3 | VIN + 0.3 | V | |
OUT | –0.3 | VIN + 0.3 | V | |
Current | OUT | Internally limited | mA | |
Temperature | Operating virtual junction, TJ | –55 | 150 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –55 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2000 | 2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | 500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage | 2.7 | 6.5 | V | |
IOUT | Output current | 0.5 | 200 | mA | |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS799Lxx | UNIT | |
---|---|---|---|
YZY (DSBGA) | |||
5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 143.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.1 | |
RθJB | Junction-to-board thermal resistance | 84.7 | |
ψJT | Junction-to-top characterization parameter | 3.8 | |
ψJB | Junction-to-board characterization parameter | 84.4 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN | Input voltage range(1) | 2.7 | 6.5 | V | |||
VOUT | Output voltage range | 5.2 | 6.2 | V | |||
Output accuracy, nominal | TJ = 25°C | –1.0% | 1.0% | ||||
Output accuracy(1)
Over VIN, IOUT, temperature |
VOUT + 0.3 V ≤ VIN ≤ 6.5 V 500 μA ≤ IOUT ≤ 200 mA |
–2.0% | ±1.0% | 2.0% | |||
ΔVO(ΔVI) | Line regulation(1) | VOUT(NOM) + 0.3 V ≤ VIN ≤ 6.5 V | 0.02 | %/V | |||
ΔVO(ΔIO) | Load regulation | 500 μA ≤ IOUT ≤ 200 mA | 0.002 | %/mA | |||
VDO | Dropout voltage (VIN = VOUT(NOM) – 0.1 V) |
VOUT ≥ 3.3 V, IOUT = 200 mA | 90 | 160 | mV | ||
ILIM | Output current limit(2) | VOUT = 0.9 × VOUT(NOM) | 220 | 340 | 600 | mA | |
IGND | Ground pin current | 500 μA ≤ IOUT ≤ 200 mA | 40 | 60 | μA | ||
ISHDN | Shutdown current (IGND) | VEN ≤ 0.4 V, 2.7 V ≤ VIN ≤ 6.5 V | 0.15 | 1.0 | μA | ||
PSRR | Power-supply rejection ratio | VIN = 6.5 V, VOUT = 2.85 V, CNR = 0.01 μF, IOUT = 100 mA |
f = 100 Hz | 70 | dB | ||
f = 1 kHz | 66 | dB | |||||
f = 10 kHz | 51 | dB | |||||
f = 100 kHz | 38 | dB | |||||
VN | Output noise voltage | BW = 10 Hz to 100 kHz | CNR = 0.01 μF | 10.5 × VOUT | μVRMS | ||
CNR = none | 94 × VOUT | μVRMS | |||||
Start-up time | VOUT = 5.7 V, RL = 28 Ω, COUT = 2.2 μF |
CNR = 0.01 μF | 90 | μs | |||
CNR = none | 95 | μs | |||||
VEN(HI) | Enable high (enabled) | 1.2 | VIN | V | |||
VEN(LO) | Enable low (shutdown) | 0 | 0.4 | V | |||
IEN(HI) | Enable pin current, enabled | VEN = VIN = 6.5 V | 0.03 | 1.0 | μA | ||
Tsd | Thermal shutdown temperature | Shutdown, temperature increasing | 165 | °C | |||
Reset, temperature decreasing | 145 | °C | |||||
TJ | Operating junction temperature | –40 | 125 | °C | |||
UVLO | Undervoltage lockout | VIN rising | 1.90 | 2.20 | 2.65 | V | |
Hysteresis | VIN falling | 70 | mV |
VIN = 6.5 V |
VIN = 6.2 V | ||
VIN = 6.5 V |
VIN = 5.95 V |
VIN = 6 V |
TPS799Axx | ||
IOUT = 250 mA |
VIN = 6.5 V |
VIN = 6.5 V | ||
VIN = 5.95 V |
VIN = 6.2 V |
VIN = 6 V |
CIN = COUT = 20 µF | IOUT = 47 mA | |
The TPS799Lxx family of low-dropout (LDO) regulators combines the high performance required of many RF and precision analog applications with ultralow current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with good supply rejection at very low headroom (VIN – VOUT). A noise-reduction pin is provided to bypass noise generated by the band-gap reference and to improve PSRR, while a quick-start circuit quickly charges this capacitor at start-up. The combination of high performance and low ground current also make these devices an excellent choice for portable applications. All versions have thermal and overcurrent protection, and are fully specified from –40°C to 125°C.
The TPS799Lxx family also features inrush current protection with an EN toggle start-up, and overshoot detection at the output. When the EN toggle is used to start the device, current limit protection is immediately activated, restricting the inrush current to the device (see Figure 16). If voltage at the output overshoots 5% from the nominal value, a pull-down resistor reduces the voltage to normal operating conditions, as shown in the Functional Block Diagram.
The TPS799Lxx internal current limit helps protect the regulator during fault conditions. In current limit mode, the output sources a fixed amount of current that is largely independent of the output voltage. For reliable operation, do not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS799Lxx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited; therefore, if extended reverse voltage operation is anticipated, external limiting may be required.
The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.
The TPS799Lxx uses a start-up circuit to quickly charge the noise reduction capacitor, CNR, if present (see the Functional Block Diagram). This circuit allows for the combination of very low output noise and fast start-up times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are appropriate for this configuration.
Note that for fastest start-up, apply VIN first, and then drive the enable pin (EN) high. If EN is tied to IN, start-up is somewhat slower. The start-up switch is closed for approximately 135 μs. To ensure that CNR is fully charged during start-up, use a 0.01-μF or smaller capacitor.
The TPS799Lxx uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly. The UVLO circuit has a deglitch feature so that undershoot transients are typically ignored on the input if these transients are less than 50 μs in duration.
Driving EN over 1.2 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing the operating current to 150 nA, nominal.
The TPS799Lxx family of LDO regulators provides high PSRR while maintaining ultralow current consumption. The family also features inrush current protection and overshoot detection at the output.
Figure 17 shows the basic circuit connections.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1-μF low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.
The TPS799Lxx is designed to be stable with standard ceramic capacitors with values of 2.2 μF or greater. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 1.0 Ω.
In most LDOs, the band gap is the dominant noise source. If a noise-reduction capacitor (CNR) is used with the TPS799Lxx, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF noise reduction capacitor. To further optimize noise, equivalent series resistance of the output capacitor can be set to approximately 0.2 Ω. This configuration maximizes phase margin in the control loop, reducing total output noise by up to 10%.
Noise can be referred to the feedback point; with CNR = 0.01 μF total noise is approximately given by Equation 1:
The TPS799Lxx uses a PMOS pass transistor to achieve a low dropout voltage. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and rDS(on) of the PMOS pass element is the input-to-output resistance. Because the PMOS device behaves like a resistor in dropout, VDO approximately scales with the output current.
As with any linear regulator, PSRR degrades as (VIN – VOUT) approaches dropout. This effect is illustrated in Figure 8 through Figure 13 in the Typical Characteristics section.
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude, but increases the duration of the transient response. The transient response of the TPS799Lxx is enhanced by an active pull-down device that engages when the output overshoots by approximately 5% or more when the device is enabled. When enabled, the pull-down device behaves like a 350-Ω resistor to ground.
The TPS799Lxx is stable with no output load. To meet the specified accuracy, a minimum load of 500 μA is required. With loads less than 500 μA at junction temperatures near 125°C, the output can drift up enough to cause the output pull-down device to turn on. The output pull-down device limits voltage drift to 5% typically; however, ground current can increase by approximately 50 μA. In typical applications, the junction cannot reach high temperatures at light loads because there is no noticeable dissipated power. The specified ground current is then valid at no load in most applications.
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the GND terminal current, and power the load.
Do place at least one 2.2-µF ceramic capacitor as close as possible to the OUT terminal of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN terminal and GND input of the regulator.
Do not exceed the absolute maximum ratings.