JAJSG59B september   2018  – december 2020 TPS7A11

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 説明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
        1. 7.3.1.1 Global Undervoltage Lockout (UVLO)
      2. 7.3.2 Active Discharge
      3. 7.3.3 Enable Pin
      4. 7.3.4 Sequencing Requirement
      5. 7.3.5 Internal Foldback Current Limit
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disable Mode
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Load Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Behavior During Transition From Dropout Into Regulation
      6. 8.1.6 Undervoltage Lockout Circuit Operation
      7. 8.1.7 Power Dissipation (PD)
      8. 8.1.8 Estimating Junction Temperature
      9. 8.1.9 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
      3. 8.2.3 Application Curve
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Spice Model
      3. 11.1.3 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Internal Foldback Current Limit

The internal foldback current limit circuit is used to protect the LDO against high-load current faults or shorting events. The foldback mechanism lowers the current limit as the output voltage decreases and limits power dissipation during short-circuit events, while still allowing for the device to operate at the rated output current; see Figure 6-12.

For example, when VOUT is 90% of VOUT(nom), the current limit is ICL (typical); however, if VOUT is forced to 0 V, the current limit is ISC (typical). In many LDOs, the foldback current limit can prevent start up into a constant-current load or a negatively-biased output. A brick-wall current limit is when there is an abrupt current stop after the current limit is reached. The foldback mechanism for this device goes into a brick-wall current limit when VOUT is 90% of VOUT(nom), thus limiting current to ICL (typical). When VOUT is approximately 0 V, current is limited to ISC (typical) in order to provide normal start up into a variety of loads. Thermal shutdown can be activated during a current-limit event because of the high power dissipation typically found in these conditions. To provide proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended.