JAJSG59B september   2018  – december 2020 TPS7A11

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
        1. 7.3.1.1 Global Undervoltage Lockout (UVLO)
      2. 7.3.2 Active Discharge
      3. 7.3.3 Enable Pin
      4. 7.3.4 Sequencing Requirement
      5. 7.3.5 Internal Foldback Current Limit
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disable Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Load Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Behavior During Transition From Dropout Into Regulation
      6. 8.1.6 Undervoltage Lockout Circuit Operation
      7. 8.1.7 Power Dissipation (PD)
      8. 8.1.8 Estimating Junction Temperature
      9. 8.1.9 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Spice Model
      3. 11.1.3 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedures

This design example is powered by a rechargeable battery that can be a building block in many portable applications. Noise-sensitive portable electronics require an efficient small-size solution for their power supply. Traditional LDOs are known for their low efficiency in contrast to the low-input, low-output voltage (LILO) LDOs such as the TPS7A11. The use of a bias rail in the TPS7A11 allows the device to operate at a lower input voltage, thus reducing the power dissipation across the die and maximizing device efficiency. Equation 7 calculates the efficiency for this design.

Equation 7. Efficiency = η = POUT/PIN ×100 % = (VOUT × IOUT) /(VIN × IIN + VBIAS × IBIAS) × 100 %

Equation 7 reduces to Equation 8 because the design example load current is much greater than the quiescent current of the bias rail.

Equation 8. Efficiency = η = (VOUT × IOUT) / (VIN × IIN) × 100%