9.1.1 Adjustable Operation

The TPS7A3001 has an output voltage range of –1.174 V to –33 V. The nominal output voltage of the device is set by two external resistors; see Figure 32.

R₁ and R₂ can be calculated for any output voltage range using the formula shown in Equation 2. To ensure stability under no load conditions, this resistive network must provide a current equal to or greater than 5 μA.

Equation 2.

If greater voltage accuracy is required, take into account the output voltage offset contributions resulting from the feedback pin current and use 0.1% tolerance resistors. Table 2 shows the 1% resistor values for several different standard output voltages.

9.1.2 Capacitor Recommendations

Use low-equivalent series resistance (ESR) capacitors for the input, output, noise reduction, and feed-forward capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. Ceramic X7R capacitors offer improved overtemperature performance, whereas ceramic X5R capacitors are the most cost-effective and are available in higher values.

9.1.3 Maximum AC Performance

To maximize noise and PSRR performance, TI recommends including a 10-μF or higher input and output capacitors, and 10-nF noise-reduction and bypass capacitors; see Figure 32. The solution illustrated in Figure 32 delivers minimum noise levels of 15.1 μV_RMS and power-supply rejection levels above 55 dB from 10 Hz to 700 kHz; see Figure 18 and Figure 26.

9.1.4 Output Noise

The TPS7A30 provides low output noise when a noise-reduction capacitor (C_NR/SS) is used.

The noise-reduction capacitor serves as a filter for the internal reference. By using a 10-nF noise reduction capacitor, the output noise is reduced by approximately 80% (from 80 μV_RMS to 17 μV_RMS); see Figure 27.

The TPS7A30 low output voltage noise makes the device an ideal solution for powering noise-sensitive circuitry.

9.1.5 Power-Supply Rejection

The 10-nF noise-reduction capacitor greatly improves TPS7A30 power-supply rejection, achieving up to 20 dB of additional power-supply rejection for frequencies between 110 Hz and 400 kHz.

Additionally, ac performance can be maximized by adding a 10-nF bypass capacitor (C_FF) from the FB pin to the OUT pin. This capacitor greatly improves power-supply rejection at lower frequencies, for the band from 10 Hz to 200 kHz; see Figure 18.

The very high power-supply rejection of the TPS7A30 makes the device a good choice for powering high-performance analog circuitry (such as operational amplifiers, ADCs, DACS, and audio amplifiers).

9.1.6 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response.

9.1.7 Post DC-DC Converter Filtering

Most of the time, the voltage rails available in a system do not match the voltage requirements for the system. These rails must be stepped up or down, depending on specific voltage requirements.

DC-DC converters are the preferred solution to step up or down a voltage rail when current consumption is not negligible. These converters offer high efficiency with minimum heat generation, but have one primary disadvantage: these converters introduce a high-frequency component (and the associated harmonics) in addition to the dc output signal.

This high-frequency component, if not filtered properly, degrades analog circuitry performance, reducing overall system accuracy and precision.

The TPS7A30 offers a wide-bandwidth, very-high power-supply rejection ratio. This specification makes the device ideal for post dc-dc converter filtering; see Figure 31. TI highly recommends using the maximum performance schematic illustrated in Figure 32. Also, verify that the fundamental frequency (and its first harmonic, if possible) is within the bandwidth of the regulator PSRR; see Figure 18.

Figure 31. Post DC-DC Converter Regulation to High-Performance Analog Circuitry

9.1.8 Audio Applications

Audio applications are extremely sensitive to any distortion and noise in the audio band from 20 Hz to 20 kHz. This stringent requirement demands clean voltage rails to power critical high-performance audio systems.

The very-high power-supply rejection ratio (> 55 dB) and low noise at the audio band of the TPS7A30 maximize performance for audio applications; see Figure 18.

9.1.9 Power for Precision Analog

One of the primary TPS7A30 applications is to provide ultralow noise voltage rails to high-performance analog circuitry in order to maximize system accuracy and precision.

In conjunction with its positive counterpart, the TPS7A49xx family of positive high-voltage linear regulators, the TPS7A30 family of negative high voltage linear regulators provides ultralow noise positive and negative voltage rails to high-performance analog circuitry (such as operational amplifiers, ADCs, DACs, and audio amplifiers).

The low noise levels at high voltages, such as ±15 V, enables clean power rails for precision analog circuitry. This characteristic allows for high-performance analog solutions to optimize the voltage range, thus maximizing system accuracy.

9.2.1 Design Requirements

The design goals are V_IN = –3 V, V_OUT = –1.2 V, and I_OUT = 150 mA, maximum. The design must optimize transient response and meet a start-up time of 14 ms. The input supply comes from a supply on the same printed circuit board (PCB). The design circuit is shown in Figure 32.

The design space consists of C_IN, C_OUT, C_NR/SS, R₁, and R₂, at T_A(max) = 75°C.

9.2.2 Detailed Design Procedure

The first step when designing with a linear regulator is to examine the maximum load current, along with the input and output voltage requirements, to determine if the device thermal and dropout voltage requirements can be met. At 150 mA, the input dropout voltage of the TPS7A30 family is a maximum of 600 mV overtemperature; therefore, the dropout headroom of 1.8 V is sufficient for operation over both input and output voltage accuracy. Dropout headroom is calculated as V_IN – V_OUT – V_DO(max), and must be greater than 0 V for reliable operation. V_DO(max) is the maximum dropout allowed, given worst-case load conditions.

The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element from the input to the output, multiplied by the maximum load current. In this example, the maximum voltage drop across in the pass element is |3 V – 1.2 V|, resulting in V_IN – V_OUT = 1.8 V. The power dissipated in the pass element is calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum power dissipated in the linear regulator is 0.273 W, and is calculated as Equation 3:

When the power dissipated in the linear regulator is known, the corresponding junction temperature rise can be calculated. To calculate the junction temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. This calculation gives the worst-case junction temperature; good thermal design can significantly reduce this number. For thermal resistance information, refer to the Thermal Information table. For this example, using the DGN package, the maximum junction temperature rise is calculated to be 17.3°C. The maximum junction temperature rise is calculated by adding the junction temperature rise to the maximum ambient temperature, which is 75°C for this example. For this example, calculate the maximum junction temperature as 92.3°C. Keep in mind that the maximum junction temperate must be below 125°C for reliable device operation. Additional ground planes, added thermal vias, and air flow all help to lower the maximum junction temperature.

Use the following equations to select the rest of the components:

To ensure stability under no-load conditions, the current through the resistor network must be greater than 5 µA, as shown in Equation 4.

Equation 4.

To set R₂ = 100 kΩ for a standard 1% value resistor, calculate R₁ as shown in Equation 5.

Equation 5.

Use a standard, 1%, 2.05-kΩ resistor for R₁.

Equation 6 calculates the start-up time, t_SS.

Equation 6.

For the soft-start to dominate the start-up conditions, ideally place the start-up time as a result of the current limit at two decades below the soft-start time (at 140 µs). C_OUT must be at least 2.2 µF for stability, as shown in Equation 7 and Equation 8.

Equation 7.

Equation 8.

For C_IN, assume that the –3-V supply has some inductance and is placed several inches away from the PCB. For this case, select a 2.2-µF ceramic input capacitor to ensure that the input impedance is negligible to the LDO control loop and to keep the physical size and cost of the capacitor low; this component is a common-value capacitor.

For better PSRR for this design, use a 10-µF input and output capacitor. To reduce the peaks from transients but slow down the recovery time, increase the output capacitor size or add additional output capacitors.

9.2.3 Application Curves

Figure 33. Capacitor-Programmable Soft-Start

Figure 35. Line Transient Response

Figure 37. Load Transient Response

Figure 34. Capacitor-Programmable Soft-Start

Figure 36. Line Transient Response