TPS7A470x 36-V, 1-A, 4-µVRMS, RF LDO Voltage Regulator

1 Features

• Input Voltage Range: +3 V to +36 V
• Output Voltage Noise:
  4 µV_RMS (10 Hz, 100 kHz)
• Power-Supply Ripple Rejection:
  • 82 dB (100 Hz)
  • ≥ 55 dB (10 Hz, 10 MHz)
• Two Output Voltage Modes:
  • ANY-OUT™ Version (User-Programmable Output via PCB Layout):
    • No External Feedback Resistors or Feed-Forward Capacitors Required
    • Output Voltage Range: +1.4 V to +20.5 V
  • Adjustable Version (TPS7A4701 only):
    • Output Voltage Range: +1.4 V to +34 V
• Output Current: 1 A
• Dropout Voltage: 307 mV at 1 A
• CMOS Logic Level-Compatible Enable Pin
• Built-In Fixed Current Limit and
  Thermal Shutdown
• Available in High-Performance Thermal Package: 5-mm × 5-mm QFN
• Operating Temperature Range:
  –40°C to 125°C

2 Applications

• Voltage-Controlled Oscillators (VCO)
• Frequency Synthesizers
• Test and Measurement
• Instrumentation, Medical, and Audio
• RX, TX, and PA Circuitry
• Supply Rails for Operational Amplifiers,
  DACs, ADCs, and Other High-Precision Analog Circuitry
• Post DC-DC Converter Regulation and
  Ripple Filtering
• Base Stations and Telecom Infrastructure
• +12-V and +24-V Industrial Buses

3 Description

The TPS7A47 is a family of positive voltage (+36 V), ultralow-noise (4 µV_RMS) low-dropout linear regulators (LDO) capable of sourcing a 1-A load.

The TPS7A4700 output voltages are user-programmable (up to 20.5 V) using a printed circuit board (PCB) layout without the need of external resistors or feed-forward capacitors, thus reducing overall component count.

The TPS7A4701 output voltage can be configured with a user-programmable PCB layout (up to 20.5 V), or adjustable (up to 34 V) with external feedback resistors.

The TPS7A47 is designed with bipolar technology primarily for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This feature makes the device ideal for powering operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry in critical applications such as medical, radio frequency (RF), and test-and-measurement.

In addition, the TPS7A47 is ideal for post dc-dc converter regulation. By filtering out the output voltage ripple inherent to dc-dc switching conversions, maximum system performance is ensured in sensitive instrumentation, test-and-measurement, audio, and RF applications.

For applications where positive and negative low-noise rails are required, consider TI's TPS7A33 family of negative high-voltage, ultralow-noise linear regulators.

1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Revision History

Changes from E Revision (January 2014) to F Revision

• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
• Reworded ninth bullet in Features listGo
• Changed polarity of op amp shown on right side of the functional block diagram Go
• Reworded second paragraph in Soft-Start And Inrush Current section Go
• Revised Capacitor Recommendations sectionGo
• Changed paragraph 2 of Dropout Voltage (VDO) section for clarity Go
• Revised paragraph 1 of Startup section Go
• Rewrote paragraph 1 of Power-Supply Rejection Ratio (PSRR) section to eliminate confusion Go
• Changed paragraph 1 of Power Supply Recommendations section Go
• Changed paragraph 1 and paragraph 4 of Power Dissipation (PD) sectionGo
• Revised paragraph 2 of Layout Guidelines section Go
• Changed second paragraph of Thermal Protection section Go

Changes from D Revision (December 2013) to E Revision

• Changed Output Voltage Noise value from 4.17 µV to 4 µV in three instances on front pageGo
• Changed 2nd and 3rd paragraphs of Description sectionGo
• Added "Thermal Pad" to pin configuration drawingGo
• Changed EN pin descriptionGo
• Changed SENSE/FB pin to be for TPS7A4701 onlyGo
• Added new row to Pin Descriptions table for SENSE pin (for TPS7A4700 only)Go
• Added new row to Pin Descriptions table for thermal padGo
• Added V_REF parameterGo
• Added TPS7A4701 device to test conditions for V_NR parameterGo
• Added Feedback Pin Current parameter to Electrical Characteristics Go
• Deleted Dropout Voltage vs Output Current graphGo
• Added EN pin to Functional Block DiagramGo
• Added sentence to ANY-OUT Programmable Output Voltage section to clarify ANY-OUT is for both devicesGo
• Changed last two paragraphs of Adjustable Operation sectionGo
• Added "TPS7A4701 Only" to Adjustable Operation section titleGo
• Deleted equation in Figure 23Go
• Changed Equation 3Go

Changes from C Revision (July 2013) to D Revision

• Changed data sheeet status from production mix to production dataGo
• Changed TPS7A4701 ESD rating from > 1 kV to 2.5 kVGo
• Changed noise reduction pin voltage parameter to show both devicesGo
• Added text clarifying V_REF typical value to last paragraph on pageGo

Changes from B Revision (April 2013) to C Revision

• Deleted TPS7A4702 preview device from data sheetGo

Changes from A Revision (July 2012) to B Revision

• Changed TPS7A47 to TPS7A4700Go
• Added TPS7A4701 and TPS7A4702 preview devices to data sheetGo
• Changed front-page figureGo
• Added FB to SENSE pin to Functional Block DiagramGo
• Added new paragraph after Table 1Go
• Added new Table 2Go
• Added Adjustable Operation sectionGo

Changes from * Revision (June 2012) to A Revision

• Moved to full production data (changes throughout document)Go

5 Pin Configuration and Functions

RGW Package

5-mm × 5-mm VQFN-20

(Top View)

6 Specifications

6.6 Typical Characteristics

At –40°C ≤ T_J ≤ 125°C; V_I = V_O(nom) + 1.0 V or V_I = 3.0 V (whichever is greater); V_EN = V_I; I_O = 0 mA; C_IN =10 µF; C_OUT = 10 µF; C_NR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless otherwise noted.

Figure 1. Noise vs Output Voltage

Figure 3. Load Regulation

Figure 5. Enable Voltage Threshold vs Temperature

Figure 7. Ground Current vs Output Current

Figure 9. Shutdown Current vs Input Voltage

Figure 11. Power-Supply Rejection Ratio vs C_NR

Figure 13. Power-Supply Rejection Ratio vs I_O

Figure 15. Power-Supply Rejection Ratio vs Dropout

Figure 17. Power-Supply Rejection Ratio vs Output Voltage

Figure 19. Load Transient

Figure 21. Startup

Figure 2. Line Regulation

Figure 4. UVLO Threshold vs Temperature

Figure 6. Quiescent Current vs Input Voltage

Figure 8. Enable Current vs Input Voltage

Figure 10. Current Limit vs Input Voltage

Figure 12. Power-Supply Rejection Ratio vs C_NR

Figure 14. Power-Supply Rejection Ratio vs Dropout

Figure 16. Power-Supply Rejection Ratio vs Dropout

Figure 18. Power-Supply Rejection Ratio vs Output Voltage

Figure 20. Line Transient

Figure 22. Noise vs Output Current

7 Detailed Description

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Internal Current Limit (I_CL)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls while load impedance decreases. Note also that when a current limit occurs while the resulting output voltage is low, excessive power is dissipated across the LDO, which results in a thermal shutdown of the output.

7.3.2 Enable (EN) And Under-Voltage Lockout (UVLO)

The TPS7A470x only turns on when both EN and UVLO are above the respective voltage thresholds. The UVLO circuit monitors input voltage (V_I) to prevent device turn-on before V_I rises above the lockout voltage. The UVLO circuit also causes a shutdown when V_I falls below lockout. The EN signal allows independent logic-level turn-on and shutdown of the LDO when the input voltage is present. EN can be connected directly to V_I if independent turn-on is not needed.

7.3.3 Soft-Start And Inrush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have achieved threshold voltage. The noise reduction capacitor serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on.

Inrush current is defined as the current through the LDO from IN to OUT during the time of the turn-on ramp up. Inrush current then consists primarily of the sum of load and charge current to the output capacitor. Inrush current can be estimated by Equation 1:

Equation 1.

where

7.5 Programming

7.5.1 ANY-OUT Programmable Output Voltage

Both devices can be used in ANY-OUT mode. For ANY-OUT operation, the TPS7A4700 and TPS7A4701 do not use external resistors to set the output voltage, but use device pins 4, 5, 6, 8, 9, 10, 11, and 12 to program the regulated output voltage. Each pin is either connected to ground (active) or is left open (floating). The ANY-OUT programming is set by Equation 2 as the sum of the internal reference voltage (V_(REF) = 1.4 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 100 mV (pin 12), 200 mV (pin 11), 400 mV (pin 10), 800 mV (pin 9), 1.6 V (pin 8), 3.2 V (pin 6), 6.4 V (pin 5), or 6.4 V (pin 4). Table 1 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to V_(REF).

Equation 2.

Table 1. ANY-OUT Programmable Output Voltage

ANY-OUT PROGRAM PINS (Active Low)	ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 4 (6P4V2)	6.4 V
Pin 5 (6P4V1)	6.4 V
Pin 6 (3P2)	3.2 V
Pin 8 (1P6)	1.6 V
Pin 9 (0P8)	800 mV
Pin 10 (0P4)	400 mV
Pin 11 (0P2)	200 mV
Pin 12 (0P1)	100 mV

Table 2 shows a list of the most common output voltages and the corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 1.4 V to 20.5 V in 100-mV steps.

Table 2. Common Output Voltages and Corresponding Pin Settings

VO (V)	PIN NAMES AND VOLTAGE PER PIN
	0P1V 100 mV	0P2V 200 mV	0P4V 400 mV	0P8V 800 mV	1P6V 1.6 V	3P2V 3.2 V	6P4V1 6.4 V	6P4V2 6.4 V
1.4	Open	Open	Open	Open	Open	Open	Open	Open
1.5	GND	Open	Open	Open	Open	Open	Open	Open
1.8	Open	Open	GND	Open	Open	Open	Open	Open
2.5	GND	GND	Open	GND	Open	Open	Open	Open
3	Open	Open	Open	Open	GND	Open	Open	Open
3.3	GND	GND	Open	Open	GND	Open	Open	Open
4.5	GND	GND	GND	GND	GND	Open	Open	Open
5	Open	Open	GND	Open	Open	GND	Open	Open
10	Open	GND	GND	Open	GND	Open	GND	Open
12	Open	GND	Open	GND	Open	GND	GND	Open
15	Open	Open	Open	GND	Open	Open	GND	GND
18	Open	GND	GND	Open	Open	GND	GND	GND
20.5	GND	GND	GND	GND	GND	GND	GND	GND

7.5.2 Adjustable Operation (TPS7A4701 Only)

The TPS7A4701 has an output voltage range of 1.4 V to 34 V. For adjustable operation, set the nominal output voltage of the device using two external resistors, as shown in Figure 23.

Figure 23. Adjustable Operation for Maximum AC Performance

R₁ and R₂ can be calculated for any output voltage within the operational range. The current through feedback resistor R₂ must be at least 5 µA to ensure stability. Additionally, the current into the FB pin (I_(FB), typically 350 nA) creates an additional output voltage offset that depends on the resistance of R₁. For high-accuracy applications, select R₂ such that the current through R₂ is at least 35 µA to minimize any effects of I_(FB) variation on the output voltage; 10 kΩ is recommended. R₁ can be calculated using Equation 3.

Equation 3.

where

• V_REF = 1.4 V
• I_FB = 350 nA

Use 0.1% tolerance resistors to minimize the effects of resistor inaccuracy on the output voltage.

Table 3 shows the resistor combinations to achieve some standard rail voltages with commercially-available 1% tolerance resistors. The resulting output voltages yield a nominal error of < 0.5%.

Table 3. Suggested Resistors for Common Voltage Rails

VOUT	R1, Calculated	R1, Closest 1% Value	R2
1.4 V	0 Ω	0 Ω	∞
1.8 V	2.782 kΩ	2.8 kΩ	9.76 kΩ
3.3 V	13.213 kΩ	13.3 kΩ	9.76 kΩ
5 V	25.650 kΩ	25.5 kΩ	10 kΩ
12 V	77.032 kΩ	76.8 kΩ	10.2 kΩ
15 V	101.733 kΩ	102 kΩ	10.5 kΩ
18 V	118.276 kΩ	118 kΩ	10 kΩ
24 V	164.238 kΩ	165 kΩ	10.2 kΩ

To achieve higher nominal accuracy, two resistors can be used in the place of R₁. Select the two resistor values such that the sum results in a value as close as possible to the calculated R₁ value.

There are several alternative ways to set the output voltage. The program pins can be pulled low using external general-purpose input/output pins (GPIOs), or can be hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. The TPS7A4701 evaluation module (EVM), available for purchase from the TI eStore, allows the output voltage to be programmed using jumpers.

8 Application and Implementation

8.2 Typical Application

Output voltage is set by grounding the appropriate control pins, as shown in Figure 24. When grounded, all control pins add a specific voltage on top of the internal reference voltage (V_(REF) = 1.4 V). For example, when grounding pins 0P1V, 0P2V, and 1P6V, the voltage values 0.1 V, 0.2 V, and 1.6 V are added to the 1.4-V internal reference voltage for V_O(nom) equal to 3.3 V, as described in the Programming section.

Figure 24. Typical Application, V_OUT = 3.3 V

8.2.1 Design Requirements

PARAMETER	DESIGN REQUIREMENT
Input Voltage	5.0 V, ±10%
Output Voltage	3.3 V, ±3%
Output Current	500 mA
Peak-to-Peak Noise, 10 Hz to 100 kHz	50 µVp-p

8.2.2 Detailed Design Procedure

8.2.2.1 Capacitor Recommendations

These LDOs are designed to be stable using low equivalent series resistance (ESR), ceramic capacitors at the input, output, and at the noise reduction pin (NR, pin 14). Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended here, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, but the use of Y5V-rated capacitors is discouraged precisely because the capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating voltage and the design engineer must be aware of these characteristics. It is recommended to apply a 50% derating of the nominal capacitance in the design.

Attention must be given to the input capacitance to minimize transient input droop during load current steps because the TPS7A470x has a very fast load transient response. Large input capacitors are necessary for good transient load response, and have no detrimental influence on the stability of the device. Note, however, that using large ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor, in combination with the wire lead inductance, creates a high-Q peaking effect during transients. For example, a 5-nH lead inductance and a 10-µF input capacitor form an LC filter with a resonance frequency of 712 kHz at the edge of the control loop bandwidth. Short, well-designed interconnect leads to the up-stream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milliohms of ESR, in parallel with the ceramic input capacitor.

8.2.2.1.1 Input and Output Capacitor Requirements

The TPS7A470x is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the input and output. Optimal noise performance is characterized using a total output capacitor value of 50 µF. Note especially that input and output capacitances must be located as near as practical to the respective input and output pins.

8.2.2.1.2 Noise Reduction Capacitor (C_NR)

The noise reduction capacitor, connected to the NR pin of the LDO, forms an RC filter for filtering out noise that might ordinarily be amplified by the control loop and appear on the output voltage. Larger capacitances, up to 1 µF, affect noise reduction at lower frequencies while also tending to further reduce noise at higher frequencies. Note that C_NR also serves a secondary purpose in programming the turn-on rise time of the output voltage and thereby controls the turn-on surge current.

8.2.2.2 Dropout Voltage (V_DO)

Generally speaking, the dropout voltage often refers to the voltage difference between the input and output voltage (V_(DO) = V_I – V_O). However, in the Electrical Characteristics V_(DO) is defined as the V_I – V_O voltage at the rated current (I_(RATED)), where the main current pass-FET is fully on in the Ohmic region of operation and is characterized by the classic R_DS(on) of the FET. V_(DO) indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain within its accuracy boundary. If the input falls below this V_(DO) limit (V_I < V_O + V_(DO)), then the output voltage decreases in order to follow the input voltage.

Dropout voltage is always determined by the R_DS(on) of the main pass-FET. Therefore, if the LDO operates below the rated current, the V_(DO) is directly proportional to the output current and can be reduced by the same factor. The R_DS(on) for the TPS7A470x can be calculated using Equation 4:

Equation 4.

8.2.2.3 Output Voltage Accuracy

The output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. This accuracy error typically includes the errors introduced by the internal reference and the load and line regulation across the full range of rated load and line operating conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage accuracy also accounts for all variations between manufacturing lots.

8.2.2.4 Startup

The startup time for the TPS7A470x depends on the output voltage and the capacitance of the C_NR capacitor. Equation 5 calculates the startup time for a typical device.

Equation 5.

where

• C_NR = capacitance of the C_NR capacitor
• V_R = V_O voltage if using the ANY-OUT configuration, or 1.4 V if using the adjustable configuration

8.2.2.5 AC Performance

AC performance of the LDO is typically understood to include power-supply rejection ratio, load step transient response, and output noise. These metrics are primarily a function of open-loop gain and bandwidth, phase margin, and reference noise.

8.2.2.5.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the dc output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 6 gives the PSRR calculation as a function of frequency where input noise voltage [V_S(IN)(f)] and output noise voltage [V_S(OUT)(f)] are understood to be purely ac signals.

Equation 6.

Noise that couples from the input to the internal reference voltage for the control loop is also a primary contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noise reduction capacitor at the NR pin of the LDO in combination with an internal filter resistor (R_SS) for optimal PSRR.

The LDO is often employed not only as a dc/dc regulator, but also to provide exceptionally clean power-supply voltages that are free of noise and ripple to power-sensitive system components. This usage is especially true for the TPS7A470x.

8.2.2.5.2 Load Step Transient Response

The load step transient response is the output voltage response by the LDO to a step change in load current whereby output voltage regulation is maintained. The worst-case response is characterized for a load step of
10 mA to 1 A (at 1 A per microsecond) and shows a classic, critically-damped response of a very stable system. The voltage response shows a small dip in the output voltage when charge is initially depleted from the output capacitor and then the output recovers as the control loop adjusts itself. The depth of the charge depletion immediately after the load step is directly proportional to the amount of output capacitance. However, to some extent, the speed of recovery is inversely proportional to that same output capacitance. In other words, larger output capacitances act to decrease any voltage dip or peak occurring during a load step but also decrease the control-loop bandwidth, thereby slowing response.

The worst-case, off-loading step characterization occurs when the current step transitions from 1 A to 0 mA. Initially, the LDO loop cannot respond fast enough to prevent a small increase in output voltage charge on the output capacitor. Because the LDO cannot sink charge current, the control loop must turn off the main pass-FET to wait for the charge to deplete, thus giving the off-load step its typical monotonic decay (which appears triangular in shape).

8.2.2.5.3 Noise

The TPS7A470x is designed, in particular, for system applications where minimizing noise on the power-supply rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based clocking circuits for instance, where minimum phase noise is all important, or in-test and measurement systems where even small power-supply noise fluctuations can distort instantaneous measurement accuracy. Because the TPS7A470x is also designed for higher voltage industrial applications, the noise characteristic is well designed to minimize any increase as a function of the output voltage.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker or 1/f noise that is a property of resistors and dominates at lower frequencies as a function of 1/f, burst noise, and avalanche noise).

To calculate the LDO RMS output noise, a spectrum analyzer must first measure the spectral noise across the bandwidth of choice (typically 10 Hz to 100 kHz in units of µV/√Hz). The RMS noise is then calculated in the usual manner as the integrated square root of the squared spectral noise over the band, then averaged by the bandwidth.

8.2.3 Application Curves

Figure 25. Startup with EN Pin rising (10 ms/DIV)

Figure 26. Output Noise Voltage, 10 Hz to 100 kHz (10 ms/DIV)