JAJSEE5B September   2017  – July 2018 TPS7A53-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      RFコンポーネントの電源
      2.      出力電圧ノイズと 周波数および出力電圧との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
      3. 7.4.3 Current Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
        1. 8.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 8.1.1.3 Feed-Forward Capacitor (CFF)
      2. 8.1.2  Soft Start and Inrush Current
      3. 8.1.3  Optimizing Noise and PSRR
      4. 8.1.4  Charge Pump Noise
      5. 8.1.5  Current Sharing
      6. 8.1.6  Adjustable Operation
      7. 8.1.7  Power-Good Operation
      8. 8.1.8  Undervoltage Lockout (UVLO) Operation
      9. 8.1.9  Dropout Voltage (VDO)
      10. 8.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 8.1.11 Load Transient Response
      12. 8.1.12 Reverse Current Protection Considerations
      13. 8.1.13 Power Dissipation (PD)
      14. 8.1.14 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
      2. 10.1.2 RTK Package — High CTE Mold Compound
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 リファレンス・デザイン
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.14 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 8 and are given in the Electrical Characteristics table.

Equation 8. TPS7A53-Q1 q_wjt-wjb_bvs204.gif

where

  • PD is the power dissipated as explained in Equation 5
  • TT is the temperature at the center-top of the device package, and
  • TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge