JAJSPA7A November   2022  – December 2022 TPS7A53A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Power-Good Output (PG)
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Output Noise
      4. 8.1.4 Estimating Junction Temperature
      5. 8.1.5 Soft Start, Sequencing, and Inrush Current
      6. 8.1.6 Power-Good Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 RTJ Package — High CTE Mold Compound
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RTJ Package (Fixed),4-mm × 4-mm, 20-Pin WQFN(Top View)
Table 5-1 Pin Functions
PIN DESCRIPTION
NAME RTJ (Fixed) TYPE
BIAS 12 I BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.3 V, VOUT = 1 V) to reduce power dissipation across the die. Using a BIAS voltage improves dc and ac performance for VIN ≤ 2.2 V. A 0.1-µF capacitor or larger must be connected between this pin and ground.
EN 14 I Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN or BIAS.
FB — I Feedback pin connected to the error amplifier. Although not required, a 10-nF, feed-forward capacitor from FB to OUT (as close to the device as possible) maximizes ac performance. Using a feed-forward capacitor can disrupt PG (power-good) functionality.
GND 8 — Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance connection.
IN 15-17 I Input supply voltage pin. A 1-µF or larger ceramic capacitor (0.5 µF or greater of capacitance) from IN to ground reduces the impedance of the input supply. Place the input capacitor as close to the input as possible.
NC 3, 5, 6, 7, 9, 10,11, 18 — No internal connection.
SS 13 — Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground enables the soft-start function.
OUT 1, 19, 20 O Regulated output pin. A 10-µF or larger ceramic capacitor (5 µF or greater of capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to the load.
PG 4 O Active-high, power-good pin. An open-drain output indicates when the output voltage reaches VIT(PG) of the target. The use of a feed-forward capacitor can disrupt PG (power-good) functionality.
SNS 2 I Sense pin connected to the error amplifier.
Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.