TPS7A90デバイスは、低ノイズ(4.7µVRMS)、低ドロップアウト(LDO)の電圧レギュレータで、500mAを供給でき、ドロップアウトは5Vでわずか100mV、5.7Vで200mVです。
TPS7A90の出力は外付けの抵抗により0.8V~5.7Vの範囲で調整可能です。TPS7A90は広い入力電圧範囲に対応し、最低1.4V、最高6.5Vで動作します。
1%の出力電圧精度(ライン、負荷、温度の変動にかかわらず)と、ソフトスタート機能による突入電流の低減から、TPS7A90は感受性の高い低電圧のアナログ・デバイス(電圧制御発振器(VCO)、アナログ/デジタル・コンバータ(ADC)、デジタル/アナログ・コンバータ(DAC)など)の電源に理想的です。
TPS7A90は、高速度通信、ビデオ、医療、試験および計測用途など、ノイズに敏感な部品に電力を供給するよう設計されています。出力ノイズが4.7µVRMSと非常に低く、広帯域のPSRR (1MHzにおいて30dB)を持つため、位相ノイズとクロック・ジッタが最小化されます。これらの機能により、クロッキング・デバイス、ADC、DACの性能が最大化されます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
TPS7A90 | WSON (10) | 2.50mm×2.50mm |
日付 | 改訂内容 | 注 |
---|---|---|
2017年6月 | * | 初版 |
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | NO. | I/O | |
EN | 7 | I | Enable pin. This pin turns the LDO on and off. If VEN ≥ VIH(EN), the regulator is enabled. If VEN ≤ VIL(EN), the regulator is disabled. The EN pin must be connected to IN if the enable function is not used. |
FB | 3 | I | Feedback pin. This pin is the input to the control loop error amplifier and is used to set the output voltage of the device. |
GND | 4 | — | Device GND. Connect to the device thermal pad. |
IN | 9, 10 | I | Input pin. A 10-µF or greater input capacitor is required. |
NR/SS | 8 | — | Noise reduction pin. Connect this pin to an external capacitor to bypass the noise generated by the internal band-gap reference. The capacitor reduces the output noise to very low levels and sets the output ramp rate to limit in-rush current. |
OUT | 1, 2 | O | Regulated output. A 10-µF or greater capacitor must be connected from this pin to GND for stability. |
PG | 5 | O | Open-drain, power-good indicator pin for the LDO output voltage. A 10-kΩ to 100-kΩ external pullup resistor is required. This pin can be left floating or connected to GND if not used. |
SS_CTRL | 6 | I | Soft-start control pin. Connect this pin either to GND or IN to change the NR/SS capacitor charging current. If a CNR/SS capacitor is not used, SS_CTRL must be connected to GND to avoid output overshoot. |
Thermal pad | Pad | — | Connect the thermal pad to the printed circuit board (PCB) ground plane. For an example layout, see Figure 42. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN, PG, EN | –0.3 | 7.0 | V |
IN, PG, EN (5% duty cycle, pulse duration ≤ 200 µs) | –0.3 | 7.5 | ||
OUT | –0.3 | VIN + 0.3 | ||
SS_CTRL | –0.3 | VIN + 0.3 | ||
NR/SS, FB | –0.3 | 3.6 | ||
Current | OUT | Internally limited | A | |
PG (sink current into the device) | 5 | mA | ||
Temperature | Operating junction, TJ | –55 | 150 | °C |
Storage, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | Input supply voltage range | 1.4 | 6.5 | V |
VOUT | Output voltage range | 0.8 | 5.7 | V |
IOUT | Output current | 0 | 0.5 | A |
CIN | Input capacitor | 10 | µF | |
COUT | Output capacitor | 10 | µF | |
CNR/SS | Noise-reduction capacitor | 0 | 10 | µF |
CFF | Feedforward capacitor | 0 | 100 | nF |
RPG | Power-good pullup resistance | 10 | 100 | kΩ |
TJ | Junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS7A90 | UNIT | |
---|---|---|---|
DSK (SON) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 56.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 46.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 29.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN | Input supply voltage range | 1.4 | 6.5 | V | ||
VREF | Reference voltage | 0.8 | V | |||
VUVLO | Input supply UVLO | VIN rising | 1.31 | 1.39 | V | |
VHYS(UVLO) | Input supply UVLO hysteresis | 290 | mV | |||
VOUT | Output voltage range | 0.8 | 5.7 | V | ||
Output voltage accuracy(1) | 1.4 V ≤ VIN ≤ 6.5 V, 5 mA ≤ IOUT ≤ 0.5 A | –1.0% | 1.0% | |||
ΔVOUT(ΔVIN) | Line regulation | 0.005 | %/V | |||
ΔVOUT(ΔIOUT) | Load regulation(2) | 5 mA ≤ IOUT ≤ 0.5 A | 0.02 | %/A | ||
VDO | Dropout voltage | 1.4 V ≤ VIN ≤ 5.0 V, IOUT = 0.5 A, VFB = 0.8 V – 3% | 100 | mV | ||
5.0 V < VIN ≤ 5.7 V, IOUT = 0.5 A, VFB = 0.8 V – 3% | 200 | |||||
ILIM | Output current limit | VOUT forced at 0.9 × VOUT(NOM), VIN = VOUT(NOM) + 300 mV |
0.8 | 1.1 | 1.5 | A |
IGND | GND pin current | VIN = 6.5 V, IOUT = 5 mA | 2.1 | 3.5 | mA | |
VIN = 1.4 V, IOUT = 0.5 A | 4 | |||||
ISDN | Shutdown GND pin current | PG = (open), VIN = 6.5 V, VEN = 0.4 V | 0.1 | 15 | µA | |
IEN | EN pin current | VIN = 6.5 V, 0 V ≤ VEN ≤ 6.5 V | –0.2 | 0.2 | µA | |
VIL(EN) | EN pin low-level input voltage (device disabled) | 0 | 0.4 | V | ||
VIH(EN) | EN pin high-level input voltage (device enabled) | 1.1 | 6.5 | V | ||
ISS_CTRL | SS_CTRL pin current | VIN = 6.5 V, 0 V ≤ VSS_CTRL ≤ 6.5 V | –0.2 | 0.2 | µA | |
VIT(PG) | PG pin threshold | For PG transitioning low with falling VOUT, expressed as a percentage of VOUT(NOM) | 82% | 88.9% | 93% | |
VHYS(PG) | PG pin hysteresis | For PG transitioning high with rising VOUT, expressed as a percentage of VOUT(NOM) | 1% | |||
VOL(PG) | PG pin low-level output voltage | VOUT < VIT(PG), IPG = –1 mA (current into device) | 0.4 | V | ||
ILKG(PG) | PG pin leakage current | VOUT > VIT(PG), VPG = 6.5 V | 1 | µA | ||
INR/SS | NR/SS pin charging current | VNR/SS = GND, VSS_CTRL = GND | 4.0 | 6.2 | 9.0 | µA |
VNR/SS = GND, VSS_CTRL = VIN | 65 | 100 | 150 | |||
IFB | FB pin leakage current | VIN = 6.5 V, VFB = 0.8 V | –100 | 100 | nA | |
PSRR | Power-supply ripple rejection | f = 500 kHz, VIN = 3.8 V, VOUT(NOM) = 3.3 V, IOUT = 250mA, CNR/SS = 10 nF, CFF = 10 nF |
39 | dB | ||
Vn | Output noise voltage | BW = 10 Hz to 100 kHz, VIN = 1.8 V, VOUT(NOM) = 0.8 V, IOUT = 0.5 A, CNR/SS = 10 nF, CFF = 10 nF |
4.7 | µVRMS | ||
Noise spectral density | f = 10 kHz, VIN = 1.8 V, VOUT(NOM) = 0.8 V, IOUT = 0.5 A, CNR/SS = 10 nF, CFF = 10 nF |
13 | nV/√Hz | |||
Rdiss | Output active discharge resistance | VEN = GND | 250 | Ω | ||
Tsd | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||
Reset, temperature decreasing | 140 |
VOUT = 0.8 V, IOUT = 500 mA, COUT = 10 µF, CNR/SS = CFF = 10 nF |
VOUT = 3.3 V, IOUT = 500 mA, COUT = 10 µF, CNR/SS = CFF = 10 nF |
VOUT = 1.2 V, VIN = VEN = 1.5 V, COUT = 10 µF, CNR/SS = CFF = 10 nF |
VOUT = 1.2 V, VIN = VEN = 1.7 V, IOUT = 500 mA, COUT = 10 µF, CFF = 10 nF |
VIN = 2.2 V, VOUT = 1.2 V, IOUT = 500 mA, CIN = COUT = 10 µF, CFF = 10 nF, VRMS BW = 10 Hz to 100 kHz |
VIN = 2.2 V, VOUT = 1.2 V, IOUT = 500 mA, CIN = 10 µF, CNR/SS = CFF = 10 nF, VRMS BW = 10 Hz to 100 kHz |
VIN = 1.4 V, VOUT = 0.8 V |
IOUT = 500 mA |
IOUT = 50 mA |
VIN = 1.4 V |
VIN = 1.4 V, IOUT = 50 mA to 500 mA to 50 mA at 1 A/µs, COUT = 10 µF, VPG = VOUT |
VIN = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUT = 0.8 V, IOUT = 500 mA, CNR/SS = CFF = 10 nF, VPG = VOUT |
VIN = 1.4 V, VPG = VOUT |
VIN = 1.4 V, VPG = VOUT |
VOUT = 1.2 V, IOUT = 500 mA, COUT = 10 µF, CNR/SS = CFF = 10 nF |
VOUT = 5 V, IOUT = 500 mA, COUT = 10 µF, CNR/SS = CFF = 10 nF |
VOUT = 3.3 V, VIN = VEN = 3.6 V, COUT = 10 µF, CNR/SS = CFF = 10 nF |
VIN = VOUT + 1.0 V, IOUT = 500 mA, CIN = COUT = 10 µF, CNR/SS = CFF = 10 nF, VRMS BW = 10 Hz to 100 kHz |
VIN = 2.2 V, VOUT = 1.2 V, IOUT = 500 mA, CIN = COUT = 10 µF, CNR/SS = 10 nF, VRMS BW = 10 Hz to 100 kHz |
VIN = 1.4 V, VOUT = 0.8 V | ||
VIN = 5.5 V |
VIN = 1.4 V |
VEN = 0.4 V |
VIN = VPG = 6.5 V |
VIN = 5.5 V, IOUT = 50 mA to 500 mA to 50 mA at 1 A/µs, COUT = 10 µF, VPG = VOUT |
VIN = 1.4 V, VPG = VOUT | ||
VIN = 1.4 V, VPG = VOUT |
The TPS7A90 is a low-noise, high PSRR, low dropout (LDO) regulator capable of sourcing a 500-mA load with only 200 mV of maximum dropout. The TPS7A90 can operate down to a 1.4-V input voltage and a 0.8-V output voltage. This combination of low-noise, high PSRR, and low dropout voltage makes the device an ideal LDO to power a multitude of loads from noise-sensitive communication components in high-speed communications applications to high-end microprocessors or field-programmable gate arrays (FPGAs).
As shown in the Functional Block Diagram section, the TPS7A90 linear regulator features a low-noise, 0.8-V internal reference that can be filtered externally to obtain even lower output noise. The internal protection circuitry (such as the undervoltage lockout) prevents the device from turning on before the input is high enough to ensure accurate regulation. Foldback current limiting is also included, allowing the output to source the rated output current when the output voltage is in regulation but reduces the allowable output current during short-circuit conditions. The internal power-good detection circuit allows down-stream supplies to be sequenced and alerts if the output voltage is below a regulation threshold.
The enable pin (EN) for the TPS7A90 is active high. The output voltage is enabled when the enable pin voltage is greater than VIH(EN) and disabled with the enable pin voltage is less than VIL(EN). If independent control of the output voltage is not needed, then connect the enable pin to the input.
The TPS7A90 has an internal pulldown MOSFET that connects a discharge resistor from VOUT to ground when the device is disabled to actively discharge the output voltage.
Dropout voltage (VDO) is defined as the VIN – VOUT voltage at the rated current (IRATED) of 500 mA, where the pass-FET is fully on and in the ohmic region of operation. VDO indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain in regulation. If the input falls below the nominal output regulation, then the output follows the input.
Dropout voltage is determined by the RDS(ON) of the pass-FET. Therefore, if the LDO operates below the rated current, then the VDO for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) for the TPS7A90:
Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. The TPS7A90 features an output voltage accuracy of 1% that includes the errors introduced by the internal reference, load regulation, and line regulation variance across the full range of rated load and line operating conditions over temperature, as specified by the Electrical Characteristics table. Output voltage accuracy also accounts for all variations between manufacturing lots.
PSRR is a measure of how well the LDO control loop rejects noise from the input source to make the dc output voltage as noise-free as possible across the frequency spectrum (usually measured from 10 Hz to 10 MHz). Even though PSRR is a loss in noise signal amplitude, the PSRR curves in the Typical Characteristics section are illustrated as positive values in decibels (dB) for convenience. Equation 2 gives the PSRR calculation as a function of frequency where input noise voltage [VIN(f)] and output noise voltage [VOUT(f)] are the amplitudes of the respective sinusoidal signals.
Noise that couples from the input to the internal reference voltage is a primary contributor to reduced PSRR performance. Using a noise-reduction capacitor is recommended to filter unwanted noise from the input voltage, which creates a low-pass filter with an internal resistor to improve PSRR performance at lower frequencies.
LDOs are often employed not only as a step-down regulators, but also to provide exceptionally clean power rails for noise-sensitive components. This usage is especially true for the TPS7A90, which features an innovative circuit to boost the PSRR between 200 kHz and 1 MHz. This boost circuit helps further filter switching noise from switching-regulators that operate in this region; see Figure 1. To achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the 100-kHz to 1-MHz band is recommended.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits. The TPS7A90 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based clocking circuits where minimum phase noise is all important, or in test and measurement systems where even small power-supply noise fluctuations can distort instantaneous measurement accuracy.
The TPS7A90 includes a low-noise reference ensuring minimal output noise in normal operation. Further improvements can be made by adding a noise-reduction capacitor (CNR/SS), a feedforward capacitor (CFF), or a combination of the two. See the Noise-Reduction and Soft-Start Capacitor (CNR/SS) and Feed-Forward Capacitor (CFF) sections for additional design information.
For more information on noise and noise measurement, see the How to Measure LDO Noise white paper.
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after the EN and UVLO thresholds are exceeded. The noise-reduction capacitor (CNR/SS) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. Larger values for the noise-reduction capacitors decrease the noise but also result in a slower output turn-on ramp rate.
The TPS7A90 features an SS_CTRL pin. When the SS_CTRL pin is grounded, the charging current for the NR/SS pin is 6.2 µA (typ); when this pin is connected to IN, the charging current for the NR/SS pin is increased to 100 µA (typ). The higher current allows the use of a much larger noise-reduction capacitor and maintains a reasonable startup time. Figure 36 shows a simplified block diagram of the soft-start circuit. The switch SW is opened to turn off the INR/SS current source after VFB reaches approximately 97% of VREF. The final 3% of VNR/SS is charged through the noise-reduction resistor (RNR), which creates an RC delay. RNR is approximately 280 kΩ and applications that require the highest accuracy when using a large value CNR/SS must take this RC delay into account.
If a noise-reduction capacitor is not used on the NR/SS pin, tying the SS_CTRL pin to the IN pin can result in output voltage overshoot of approximately 10%. This overshoot is minimized by either connecting the SS_CTRL pin to GND or using a capacitor on the NR/SS pin.
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the feedback pin voltage falls below the PG threshold voltage (VIT(PG)), the PG pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external reset device such as the TPS3890 is also recommended in applications where high accuracy is needed or in applications where microprocessor induced resets are needed.
When using a feed-forward capacitor (CFF), the time constant for the LDO startup is increased whereas the power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. To avoid this issue and to receive a valid PG output, make sure that the time constant of both the LDO startup and the power-good output are matching, which can be done by adding a capacitor in parallel with the power-good pullup resistor. For more information, see the application report Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator.
The state of PG is only valid when the device is operating above the minimum input voltage of the device and power-good is asserted regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO hysteresis. Figure 37 illustrates a simplified block diagram of the power-good circuit. When the input voltage falls below approximately 0.8 V, there is not enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output is pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.
The TPS7A90 has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has approximately 290 mV of hysteresis.
The UVLO circuit responds quickly to glitches on VIN and disables the output of the device if this rail starts to collapse too quickly. Use an input capacitor that is large enough to slow input transients to less then two volts per microsecond.
The internal current-limit circuit is used to protect the LDO against transient high-load current faults or shorting events. The LDO is not designed to operate in current limit under steady-state conditions. During an overcurrent event where the output voltage is pulled 10% below the regulated output voltage, the LDO sources a constant current as specified in the Electrical Characteristics table. When the output voltage falls, the amount of output current is reduced to better protect the device. During a hard short-circuit event, the current is reduced to approximately 1.45 A. See Figure 12 in the Typical Characteristics section for more information about the current-limit foldback behavior. However, when a current-limit event occurs, the LDO begins to heat up because of the increase in power dissipation. The increase in heat can trigger the integrated thermal shutdown protection circuit.
The TPS7A90 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the output turns on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.
The internal protection circuitry of the TPS7A90 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A90 into thermal shutdown degrades device reliability.
For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown must occur at least 35°C above the maximum expected ambient temperature condition for the application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
OPERATING MODE | PARAMETER | |||
---|---|---|---|---|
VIN | EN | IOUT | TJ | |
Normal(1) | VIN > VOUT(nom) + VDO | VEN > VIH(EN) | IOUT < ICL | TJ < Tsd |
Dropout(1) | VIN < VOUT(nom) + VDO | VEN > VIH(EN) | IOUT < ICL | TJ < Tsd |
Disabled(2) | VIN < VUVLO | VEN < VIL(EN) | — | TJ > Tsd |
The device regulates to the nominal output voltage when all of the following conditions are met:
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible. When the input voltage returns to VIN ≥ VOUT(NOM) + VDO, VOUT can overshoot for a short period of time if the input voltage slew rate is greater than 0.1 V/µs.
The output of the TPS7A90 can be shutdown by forcing the enable pin below 0.4 V. When disabled, the pass device is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal resistor from the output to ground.