JAJSMN7C september   2021  – june 2023 TPS7A94

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

8.1.9 Optimizing Noise and PSRR

Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated LDO output). Noise can easily be noticed in audio as a hissing or popping sound. Noise produced from an external circuit or the 50- to 60-hertz power-line noise (spikes), along with the harmonics, is an excellent representative of extrinsic noise. Intrinsic noise is produced by components within the device circuitry, such as resistors and transistors. The two dominating sources of intrinsic noise are the error amplifier and the internal reference voltage (VNR/SS). Extrinsic noise, including the switching mode power-supply ac ripple voltage, coupled onto the input supply of the LDO is attenuated by the LDO power-supply rejection ratio, or PSRR. PSRR is a measurement of the noise attenuation from the input to the output of the LDO.

Optimize the intrinsic noise and PSRR by carefully selecting:

  • CNR/SS for the low-frequency range up to the device bandwidth
  • COUT for the high-frequency range close to and higher than the device bandwidth
  • Operating headroom, VIN – VOUT (VDO), mainly for the low-frequency range up to the device bandwidth, but also for higher frequencies to a lesser effect

These behaviors are described in the Typical Characteristics curves.

Figure 8-14 and Figure 8-15 show the measured 10-Hz to 100-kHz RMS noise for a 3.3-V device output voltage with a 0.5-V headroom for different CNR/SS and COUT capacitors and a 1-A load current. Table 8-3 lists the typical output noise for these capacitors.

GUID-20220208-SS0I-JKPL-WLWD-SJGCMDCPC459-low.pngFigure 8-14 PSRR vs Frequency and IOUT for VOUT = 3.3 V, COUT = 10 μF
GUID-20220304-SS0I-MTHP-BSN8-3C4Q6C86PMSK-low.pngFigure 8-15 PSRR vs Frequency and IOUT for VOUT = 3.3 V, COUT = 4.7 μF || 4.7 μF|| 1.0 μF
Table 8-3 Typical Output Noise for 3.3-VOUT vs CNR/SS, COUT, and Typical Start-Up Time
Vn (μVRMS), 10-Hz to 100-kHz BW CNR/SS (µF) COUT (µF) START-UP TIME (ms)
0.98 1 10 3.73
0.62 2.2 10 6.21
0.46 4.7 10 13.97
0.42 10 10 28.21

PSRR can be viewed as being simply the ratio of the output capacitor impedance by the LDO output impedance. At low frequency, the output impedance is very low whereas the output impedance of the capacitor is high, resulting in high PSRR. As the frequency increases, the output capacitor impedance reduces and reaches a minima set by the ESR.

As shown in Figure 8-14 and Figure 8-15, and in order to achieve high PSRR at high frequencies, ensure that the output capacitor ESR and ESL are minimal. These figures compare the use of a single 10-μF output capacitor with a 4.7-μF || 4.7-μF || 1.0-μF implementation. Notice that below 200 kHz, there is no impact on performance but above 200 kHz, the PSRR improves by 5 dB to 7 dB.

Minimizing the ESR, ESL generated resonance point in the output capacitance allows for a smoother transition between the LDO active PSRR component to the passive PSRR of the capacitors.