JAJSMN7C september   2021  – june 2023 TPS7A94

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

8.1.6 Adjusting the Factory-Programmed Current Limit

The current limit is a brick-wall scheme and the factory-programmed current limit value can be programmed to a set of discrete value (100%, 80%, or 60% of the default value), as specified in the Electrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical Characteristics table. This adjustment can be done by changing the input impedance of the FB_PG pin represented by the parallel resistance of RFB_PG(TOP) || RFB_PG(BOTTOM). The FB_PG pin has dual functionality: adjusting the ICL value and setting the power-good (PG) assert threshold.

Prior to start up, the input impedance of the FB_PG pin is sampled and the ICL value is adjusted based on the input impedance.

Note:

The current limit programmability is dependent on the output voltage. For voltages below 0.4 V, the current limit cannot be programmed. For voltages between 0.4 V and 1.2 V, the current limit cannot be adjusted and is always set to 100%. Table 8-1 describes this behavior.

Table 8-1 Programmable Current Limit vs Output Voltage
NOMINAL OUTPUT VOLTAGE (V) RFB_PG(BOTTOM) (kΩ) RFB_PG(TOP) (kΩ) ICL SETTING (%)
VOUT(nom) ≥ 1.2 V
RFB_PG(BOTTOM) = 0.2 V / 16 μA
RFB_PG(TOP) = RFB_PG(BOTTOM) × ( VOUT(nom) / 0.2 V × K – 1)
with K = PG threshold (%VOUT)		 100
RFB_PG(BOTTOM) = 0.2 V / 4 μA
 80
RFB_PG(BOTTOM) = 0.2 V / 2 μA
 60
0.4 V ≤ VOUT(nom) < 1.2 V
RFB_PG(BOTTOM) = 0.2 V / 6 μA
 100
VOUT(nom) < 0.4 V N/A N/A N/A

Table 8-2 provides values for various output voltages using 1% resistors.

Table 8-2 Programmable Current Limit Voltage-Divider Current Settings
NOMINAL OUTPUT VOLTAGE (V) RFB_PG(BOTTOM) (kΩ) RFB_PG(TOP) (kΩ) ICL SETTING (%) PG THRESHOLD (%)
VOUT(nom) = 1.2 V 12.4 51.1 100 85
49.9 205 80 85
100 412 60 85
VOUT(nom) = 3.3 V 12.4 187 100 95
49.9 732 80 95
100 1470 60 95
VOUT(nom) = 5.1 V 12.4 287 100 95
49.9 1150 80 95
100 2320 60 95

Figure 8-9 shows the different ICL settings for a nominal 3.3-V output voltage.

GUID-20210406-CA0I-RN57-5QNW-89ZHXCXPWG8S-low.gif Figure 8-9 Programmable Current Limit Behavior (Typical) for a 3.3-VOUT(nom)