JAJSM29A april   2023  – july 2023 TPS7A96

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft-Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLOs
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A96EVM-106 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating temperature range (TJ = –40°C to +125°C), VIN(NOM) = VOUT(NOM) + 0.5 V, VOUT(NOM) = 3.3 V, IOUT = 1 mA,
VEN = 1.8 V, CIN = COUT = 10 μF, CNR/SS = 0 nF, and PG pin pulled up to VIN with 100 kΩ (4) (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range 1.9 5.7 V
VUVLO Input supply UVLO VIN rising, no load 1.6 1.7 V
VHYS(UVLO) Input supply UVLO hysteresis No load 40 53 mV
INR/SS NR/SS pin current VIN = 1.9 V, IOUT = 1 mA, VOUT = 1.2 V 150 µA
1.9 V ≤ VIN ≤ 5.5 V, 0.4 V ≤ VOUT < 1.2 V, 1 mA ≤ IOUT ≤ 2A –1.5 1.5 %
1.9 V ≤ VIN ≤ 5.5 V, 1.2 V ≤ VOUT ≤ 5.1 V, 1 mA ≤ IOUT ≤ 2A –1 1
IFAST_SS NR/SS fast start-up charging current VNR/SS = GND, VIN ≥ 2.5 V, VFB_PG < 0.2 V, IOUT = 0 mA 2.1 mA
VNR/SS = GND, VIN = 1.9 V, VFB_PG < 0.2 V, IOUT = 0 mA 1.5
VOUT Output voltage range 0 5.5 V
VOS Output offset voltage (VNR/SS – VOUT) 1.9 V ≤ VIN ≤ 5.7 V, 1.2 V ≤ VOUT ≤ 5.1 V,
1 mA ≤ IOUT ≤ 2 A		 –2 ±0.1 2 mV
1.9 V ≤ VIN ≤ 5.7 V, 0.4 V ≤ VOUT < 1.2 V,
1 mA ≤ IOUT ≤ 2 A		 –5 ±0.2 5
ΔVOUT(ΔVIN) Line regulation: ΔINR/SS 0.4 V ≤ VOUT < 1.2 V, IOUT = 1 mA,
VIN = (VOUT + 0.5 V) to 5.7 V		 –0.9 nA/V
VOUT = 1.2 V and VOUT = 3.3 V, IOUT = 1mA,
VIN = (VOUT + 0.5V) to 5.7 V		 2
Line regulation: ΔVOS 0.4 V ≤ VOUT < 1.2 V, IOUT = 1 mA,
VIN = (VOUT + 0.5 V) to 5.7 V		 –4.5 µV/V
VOUT = 1.2 V & VOUT = 3.3 V, IOUT = 1 mA,
VIN = (VOUT + 0.5 V) to 5.7 V		 2.1
ΔVOUT(ΔIOUT) Load regulation: ΔINR/SS(1) VIN = 1.9 V, VOUT = 1.2 V, 1 mA ≤ IOUT ≤ 2 A 2.3 nA
VIN = 3.8 V, VOUT = 3.3 V, 1 mA ≤ IOUT ≤ 2 A –3.6
VIN = 5.6 V, VOUT = 5.1 V, 1 mA ≤ IOUT ≤ 2 A –21
Load regulation: ΔVOS(1) VIN = VOUT(NOM) + 0.5 V, 1.2V ≤ VOUT ≤ 5.1 V, 1 mA ≤ IOUT ≤ 2 A 0.03 mV
ΔINR/SS(ΔVNR/SS) Change in INR/SS vs VNR/SS 0.4 V ≤ VNR/SS ≤ 1.5 V, VIN = 5.7 V, IOUT = 1 mA 6.3 nA
1.5 V ≤ VNR/SS ≤ 5 V, VIN = 5.7 V, IOUT = 1 mA –3.3
ΔVOS(ΔVNR/SS) Change in VOS vs VNR/SS 0.4 V ≤ VNR/SS ≤ 1.5 V, VIN = 5.7 V, IOUT = 1 mA 0.033 mV
1.5 V ≤ VNR/SS ≤ 5 V, VIN = 5.7 V, IOUT = 1 mA 0.013
VDO Dropout voltage(2) 1.9 V ≤ VIN < 2.0 V, IOUT = 1 mA,
VOUT = 99% x VOUT(NOM)		 160 mV
1.9 V ≤ VIN < 2.4 V, IOUT = 2 A,
VOUT = 99% x VOUT(NOM)		 215 350
VIN ≥ 2.0 V, IOUT = 1 mA, 
VOUT = 99% x VOUT(NOM)		 140
VIN ≥ 2.4 V, IOUT = 2 A, 
VOUT = 99% x VOUT(NOM)		 160 250
ILIM Output current limit VOUT forced at 90% of VOUT(NOM),
VIN = VOUT(NOM) + 200 mV or VIN = 1.9 V whichever is greater, VOUT(NOM) ≥ 1.2 V, RPGFB-to-GND ≤ 12.5 kΩ (±1%)		 2.4 2.6 2.8 A
VOUT forced at 90% of VOUT(NOM),
VIN = VOUT(NOM) + 200 mV or VIN = 1.9 V whichever is greater, VOUT(NOM) ≥ 1.2 V, RPGFB-to-GND = 50 kΩ (±1%)		 1.92 2.07 2.24
VOUT forced at 90% of VOUT(NOM),
VIN = VOUT(NOM) + 200 mV or VIN = 1.9 V whichever is greater, VOUT(NOM) ≥ 1.2 V, RPGFB-to-GND = 100 kΩ (±1%)		 1.44 1.55 1.68
ΔISC Short-circuit current-limit variation (3) VIN = VOUT(NOM) + 200 mV or VIN = 1.9 V whichever is greater, VOUT = 0 V 4.56 %
IGND GND pin current VIN = 5.7 V, VOUT = 5.1 V, IOUT = 0.1 mA 8 15 22 mA
VIN = 1.9 V, IOUT = 2 A, VOUT = 1.2 V 40 49 59
ISHDN Shutdown GND pin current PG = (open), VIN = 5.7 V, VEN_UV  = 0.4 V 0.1 30 µA
IEN_UV EN_UV pin current VIN = 5.7 V, 0 V ≤ VEN_UV ≤ 5.5 V –1 1 µA
VIH(EN_UV) EN_UV trip point rising (turn-on) VIN = 1.9 V, no load 1.20 1.22 1.25 V
VHYS(EN_UV) EN_UV trip point hysteresis VIN = 1.9 V, no load 150 mV
tPGDH PG delay time rising Time from VOUT crossing PG threshold% to PG reaching 20% of its value 1.1 ms
tPGDL PG delay time falling Time from 90% of VOUT to 80% of PG 3 µs
VFB_PG FB_PG pin trip point (rising) 1.9 V ≤ VIN ≤ 5.7 V 0.19 0.2 0.21 V
VHYS(FB_PG) FB_PG pin hysteresis 1.9 V ≤ VIN ≤ 5.7 V 6 mV
VOL(PG) PG pin low-level output voltage VIN = 1.9 V, VOUT < VFB_PG(threshold), IPG = –1 mA (current into device) 0.4 V
IPG(LKG) PG pin leakage current VIN = 5.7 V, VOUT > VFB_PG(threshold), VPG = 5.5 V 1 µA
IFB_PG FB_PG pin leakage current VIN = 5.7 V, VFB_PG = 0.2 V –100 100 nA
PSRR Power-supply ripple rejection f = 1 MHz, VIN = 3.8 V, VOUT(NOM) = 3.3 V,
IOUT = 1.5 A, CNR/SS = 4.7 µF		 30 dB
Vn Output noise voltage BW = 10 Hz to 100 kHz, 1.9 V ≤ VIN ≤ 5.7 V,
VOUT(NOM) = 1.2 V, IOUT = 2.0 A, CNR/SS = 4.7 µF		 0.5 µVRMS
BW = 10 Hz to 100 kHz, VIN = 2 V, VOUT(NOM) = 0.8 V,
IOUT = 2.0 A, CNR/SS = 4.7 µF		 0.835
Noise spectral density f = 100 Hz, 1.9 V ≤VIN ≤ 5.7 V, VOUT(NOM) = 1.2 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF		 6.6 nV/√Hz
f = 1 kHz, 1.9 V ≤VIN ≤ 5.7 V, VOUT(NOM) = 1.2 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF		 1.3
f = 10 kHz, 1.9 V ≤ VIN ≤ 5.7 V, VOUT(NOM) = 1.2 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF		 1.1
RPULLDOWN_NRSS NRSS active discharge resistance VIN = 1.9 V, VEN_UV = GND 15 Ω
RPULLDOWN Output active discharge resistance VIN = 1.9 V, VEN_UV = GND 195 Ω
TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing 175 °C
TSD(reset) Thermal shutdown reset temperature Reset, temperature decreasing 160
(1) The device is not tested under conditions where VIN > VOUT(NOM) + 2.5 V and IOUT > 1.5 A because the junction temperature is higher than +125°C. Also, this accuracy specification does not apply on any application condition that exceeds the maximum junction temperature.
(2) Measured when output voltage drops 1% below targeted value.
(3) Brick-wall current limit: ICL_% = (ISC - ICL_@0.9xVOUT) / ICL_@0.9xVOUT x 100.
(4) Additional information on setting the PG pullup resistor can be found in the application section.