JAJSRB5A September   2023  – November 2023 TPS7B4256-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Tracker Output Voltage (VOUT)
        1. 6.3.1.1 Output Voltage Equal to Reference Voltage
        2. 6.3.1.2 Output Voltage Less Than the Reference Voltage
        3. 6.3.1.3 Output Voltage Larger Than the Reference Voltage
      2. 6.3.2 Reverse Current Protection
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Current Limit
      6. 6.3.6 Output Short to Battery
      7. 6.3.7 Tracking Regulator With an Enable Circuit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Operation With VIN < 3 V
      4. 6.4.4 Disable With ADJ/EN Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Dropout Voltage
      2. 7.1.2 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Selection
        2. 7.2.2.2 Feedback Resistor Selection
        3. 7.2.2.3 Feedforward Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package Mounting
        2. 7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
        3. 7.4.1.3 Power Dissipation and Thermal Considerations
        4. 7.4.1.4 Thermal Performance Versus Copper Area
        5. 7.4.1.5 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.3 Feedforward Capacitor

A feedforward capacitor (CFF) is recommended to be connected between the OUT pin and the FB pin. CFF improves transient, noise, and PSRR performance. A higher capacitance CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.

As shown in Figure 7-2, poor layout practices and using long traces at the FB pin results in the formation of a parasitic capacitor (CFB).

GUID-20231024-SS0I-HTJZ-SR4D-JL9SQGD7G7Z9-low.svg Figure 7-2 Formation of Parasitic Capacitor at the FB Pin

CFB, along with the feedback resistors R1 and R2 can result in the formation of an uncompensated pole in the transfer function of the loop gain. A CFB value as small as 7 pF can cause the parasitic pole frequency, given by Equation 7, to fall within the bandwidth of the LDO and result in instability.

Equation 7. f P =   1 2 × π × C F B × R 1 ∥ R 2

Adding a feedforward capacitor (CFF), as shown in Figure 7-3, creates a zero in the loop gain transfer function that can compensate for the parasitic pole created by CFB. Equation 8 and Equation 9 calculate the pole and zero frequencies.

GUID-20231024-SS0I-DLRH-HSLN-WL00DQHBCK0J-low.svg Figure 7-3 Feedforward Capacitor Can Compensate the Effects of the Parasitic Capacitor
Equation 8. f P =   1 2 × π × R 1 ∥ R 2 × C F F + C F B
Equation 9. f Z =   1 2 × π × C F F × R 1

The CFF value that makes fP equal to fZ, and result in a pole-zero cancellation, depends on the values of CFB and the feedback resistors used in the application. Alternatively, if the feedforward capacitor is selected so that CFF ≫ CFB, then the pole and zero frequencies given by Equation 8 and Equation 9 are related as:

Equation 10. f p f z   ≈   1 +   R 1 R 2   =   V O U T V A D J / E N

In most applications, particularly where a 3.3-V or 5-V VOUT is generated, this ratio is not very large, implying that the frequencies are located close to each other and therefore the parasitic pole is compensated. Even for large VOUT values, where this ratio can be as large as 20, a CFF value in the range 100 pF ≤ CFF ≤ 10 nF typically helps prevent instability caused by the parasitic capacitance on the feedback node.

Following good layout practices, as described in the Layout Guidelines section and in the TRKRLDOEVM-119 General-Purpose Tracker LDO Evaluation Module user guide, helps minimize the parasitic feedback pin capacitance to values that prevent the resulting parasitic pole from causing instability.