JAJSRB5A September   2023  – November 2023 TPS7B4256-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Tracker Output Voltage (VOUT)
        1. 6.3.1.1 Output Voltage Equal to Reference Voltage
        2. 6.3.1.2 Output Voltage Less Than the Reference Voltage
        3. 6.3.1.3 Output Voltage Larger Than the Reference Voltage
      2. 6.3.2 Reverse Current Protection
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Current Limit
      6. 6.3.6 Output Short to Battery
      7. 6.3.7 Tracking Regulator With an Enable Circuit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Operation With VIN < 3 V
      4. 6.4.4 Disable With ADJ/EN Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Dropout Voltage
      2. 7.1.2 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Selection
        2. 7.2.2.2 Feedback Resistor Selection
        3. 7.2.2.3 Feedforward Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package Mounting
        2. 7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
        3. 7.4.1.3 Power Dissipation and Thermal Considerations
        4. 7.4.1.4 Thermal Performance Versus Copper Area
        5. 7.4.1.5 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4 Thermal Information

THERMAL METRIC(1)(2) TPS7B4256-Q1
D (SOIC) DDA (HSOIC) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 100.9 53.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.2 75.2 °C/W
RθJB Junction-to-board thermal resistance 38.3 28.1 °C/W
ψJT Junction-to-top characterization parameter 8.4 10.9 °C/W
ψJB Junction-to-board characterization parameter 37.9 28 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance - 13.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) The thermal data is based on the JEDEC standard high-K board layout, JESD 51-7. This is a two-signal, two-plane, four-layer board with 2-oz. copper on the external layers. The copper pad is soldered to the thermal land pattern. Also, correct attachment procedure must be incorporated.