JAJSD18C February   2017  – December 2022

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Current Limit
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Integrated Watchdog
        1. 7.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)
        2. 7.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)
        3. 7.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
        4. 7.3.7.4 ROSC Status Detection (ROSC)
        5. 7.3.7.5 Watchdog Enable (PG and WD_EN)
        6. 7.3.7.6 Watchdog Initialization
        7. 7.3.7.7 Window Watchdog Operation (WTS = Low)
        8. 7.3.7.8 Standard Watchdog Operation (WTS = High)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With Input Voltage Lower Than 4 V
      2. 7.4.2 Operation With Input Voltage Higher Than 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Power-Good Threshold
        4. 8.2.2.4 Power-Good Delay Period
        5. 8.2.2.5 Watchdog Setup
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VIN = 14 V, COUT ≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VIN Input voltage 4 40 V
I(SLEEP) Input sleep current EN = OFF 4 µA
I(Q) Input quiescent current VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3-V VOUT; EN = ON; watchdog disabled; IOUT < 1 mA; TJ < 80°C 19 29.6 µA
VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3-V VOUT; EN = ON; watchdog enabled; IOUT < 1 mA 28 42
VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3-V VOUT; EN = ON; watchdog enabled; IOUT < 100 mA 78 98
V(UVLO) Undervoltage lockout, falling Ramp VIN down until output is turned off 2.6 V
V(UVLO_HYST) UVLO hysteresis 0.5 V
ENABLE INPUT, WATCHDOG TYPE SELECTION AND FSEL (EN, WTS, AND FSEL)
VIL Low-level input voltage 0.7 V
VIH High-level input voltage 2 V
Vhys Hysteresis 150 mV
WATCHDOG ENABLE (WD_EN PIN)
VIL Low-level input threshold voltage for watchdog enable pin Watchdog enabled 0.7 V
VIH High-level input threshold voltage for watchdog enable pin Watchdog disabled 2 V
IWD_EN Pulldown current for watchdog enable pin VWD_EN = 5 V 3 µA
REGULATED OUTPUT (OUT)
VOUT Regulated output VIN = 5.6 V to 40 V for fixed 5-V VOUT, VIN = 4 V to 40 V for fixed 3.3-V VOUT, IOUT = 0 to 300 mA, –40°C ≤ TJ ≤ 125°C –2% 2%
VIN = 5.6 V to 40 V for fixed 5-V VOUT; VIN = 4 V to 40 V for fixed 3.3-V VOUT; IOUT = 0 to 300 mA –2.5% 2.5%
ΔVOUT(ΔVIN) Line regulation VIN = 5.6 V to 40 V 10 mV
ΔVOUT(ΔIOUT) Load regulation IOUT = 1 mA to 300 mA 20 mV
V(dropout) Dropout voltage (VIN – VOUT) IOUT = 300 mA(2) 300 400 mV
IOUT = 200 mA(2) 170 325
IOUT Output current VOUT in regulation 0 300 mA
I(LIM) Output current limit VOUT shorted to ground, VIN = 5.6 V to 40 V 301 680 1000 mA
PSRR Power-supply ripple rejection(1) IOUT = 100 mA; COUT = 10 µF; frequency (f) = 100 Hz 60 dB
IOUT = 100 mA; COUT = 10 µF; frequency (f) = 100 kHz 40
POWER-GOOD (PG, PGADJ)
VOL(PG) PG output, low voltage IOL = 5 mA, PG pulled low 0.4 V
Ilkg(PG) PG pin leakage current PG pulled to VOUT through a 10-kΩ resistor 1 µA
V(PG_TH) Default power-good threshold VOUT powered above the internally set tolerance, PGADJ pin shorted to ground 89.6 91.6 93.6 % of VOUT
V(PG_HYST) Power-good hysteresis VOUT falling below the internally set tolerance hysteresis 2 % of VOUT
PGADJ
V(PGADJ_TH) Switching voltage for the power-good adjust pin VOUT is falling 1.067 1.1 1.133 V
POWER-GOOD DELAY
I(DLY_CHG) DELAY capacitor charging current 3 5 10 µA
V(DLY_TH) DELAY pin threshold to release PG high Voltage at DELAY pin is ramped up 0.95 1 1.05 V
I(DLY_DIS) DELAY capacitor discharging current VDELAY = 1 V 0.5 mA
CURRENT VOLTAGE REFERENCE (ROSC)
VROSC Voltage reference 0.95 1 1.05 V
WATCHDOG (WD, WDO, WRS)
VIL Low-level threshold voltage for the watchdog input and window-ratio select For WD and WRS pins 30 % of VOUT
VIH High-level threshold voltage for the watchdog input and window-ratio select For WD and WRS pins 70 % of VOUT
V(HYST) Hysteresis 10 % of VOUT
IWD Pulldown current for the WD pin VWDO = 5 V 2 4 µA
VOL Low-levlel watchdog output IWDO = 5 mA 0.4 V
Ilkg WDO pin leakage current WDO pin pulled to VOUT through 10-kΩ resistor 1 µA
OPERATING TEMPERATURE RANGE
TJ Junction temperature –40 150 °C
T(SD) Junction shutdown temperature 175 °C
T(HYST) Hysteresis of thermal shutdown 25 °C
(1) Design information – not tested, determined by characterization.
(2) This test is done with VOUT in regulation, measuring the VIN – VOUT when VOUT drops by 100 mV from the rated output voltage at the specified load.