JAJSC12D October   2013  – April 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      可変出力オプション
      2.      固定出力オプション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN)
      2. 9.3.2 Regulated Output (VOUT)
      3. 9.3.3 Power-On-Reset (RESET)
      4. 9.3.4 Reset Delay Timer (DELAY)
      5. 9.3.5 Adjustable Output Voltage (ADJ for TPS7B6701)
      6. 9.3.6 Undervoltage Shutdown
      7. 9.3.7 Thermal Shutdown
      8. 9.3.8 Thermal Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation With VIN < 4 V
      2. 9.4.2 Operation With EN Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Dissipation and Thermal Considerations
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Dropout Recovery
      1. 11.1.1 LDO Dropout Recovery Explained
      2. 11.1.2 TPS7B67xx-Q1 Dropout During Startup
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Enhanced Thermal Pad
      2. 12.1.2 Package Mounting
      3. 12.1.3 Board Layout Recommendations to Improve PSRR and Noise Performance
      4. 12.1.4 Additional Layout Considerations
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

VI = 14 V, 1 mΩ < ESR < 20 Ω, TJ = –40°C to 150°C unless otherwise stated
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (VIN)
VI Input voltage Fixed 3.3-V output, IO = 0 mA to 450 mA 4 40 V
Fixed 5-V output, IO = 0 mA to 450 mA 5.5 40
Adjustable output, VO ≤ 3.5 V, IO = 0 mA to 450 mA 4 40
Adjustable output, VO ≥ 3.5 V, IO = 0 mA to 450 mA VO + 0.5 40
IQ Quiescent current VI = 5.5 V to 40 V (fixed 5 V), 4 V to 40 V (fixed 3.3 V),
EN = ON, IO = 0.2 mA 		15 25 µA
VI = 4 V to 40 V (adjustable version, VO = 1.5 V),
EN = ON, IO = 0.2 mA 		15 25
VI = 18.5 V to 40 V (adjustable version, VO = 18 V),
EN = ON, IO = 0.2 mA 		25 35
ISleep Input sleep current NO load current and EN = OFF 4 µA
IEN EN pin current EN = 40 V 1 µA
Vbg Band gap Reference voltage for ADJ –2% 1.233 2% V
VINUVLO Undervoltage detection Ramp VI down until output is turned OFF 2.6 V
UVLOHys Undervoltage detection hysteresis 1 V
ENABLE INPUT (EN)
VIL Logic input low level 0 0.4 V
VIH Logic input high level 1.7 V
REGULATED OUTPUT (VOUT)
VO Regulated output(1) VI = VO + 0.5 V to 40 V and VI ≥ 4 V, IO = 0 mA to 450 mA –2% 2%
ΔVO(ΔVI) Line regulation VI = VO + 1 V to 40 V and VI ≥ 4 V, IO = 100 mA, ∆VO 10 mV
ΔVO(ΔIL) Load regulation IO = 1 mA to 450 mA, ∆VO 10 mV
Vdropout Dropout voltage VI – VO, IO = 400 mA 240 450 mV
VI – VO, IO = 200 mA 160 300
IO Output current VO in regulation 0 450 mA
Ilreg-CL Output current-limit VO short to ground 140 360 mA
VO = VO typical × 0.9 470 850
PSRR Power-supply ripple rejection(2) IL = 100 mA, CO = 22 µF Freq = 100 Hz 60 dB
Freq = 100 kHz 40
RESET
VOL Reset pulled low IOL = 0.5 mA 0.4 V
IOH Reset pulled VOUT through
10-kΩ resistor		 Leakage current 1 µA
VTH-(POR) Power-on-reset threshold VO power-up set tolerance 89.6 91.6 93.6 % of VOUT
Vhys Hysteresis VO power-down set tolerance 2 % of VOUT
RESET DELAY
IChg Delay capacitor charging current Rdelay = 0 V 6 9.5 14 µA
Vth Threshold to release RESET high 1 V
OPERATING TEMPERATURE RANGE
TJ Junction temperature –40 150 °C
Tsd Junction shutdown temperature 175 °C
Thys Hysteresis of thermal shutdown 24 °C
(1) External resistor divider variation is not considered.
(2) Design information — not tested, ensured by characterization.
(3) This information only will NOT be tested in production. The equation is based on:
(C × 1) / (9.5 × 10–6) = tDelay (delay time)
Where
tab● C = delay capacitor value capacitance
tab● C range = 100 pf to 500 nF