SLVSCJ8B November   2014  – January 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input (IN)
      2. 8.3.2 Output (OUT)
      3. 8.3.3 Output Capacitor Selection
      4. 8.3.4 Low-Voltage Tracking
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VI Less Than 4 V
      2. 8.4.2 Operation With VI Greater Than 4 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitor
        2. 9.2.2.2 Output Capacitor
        3. 9.2.2.3 Power Dissipation and Thermal Considerations
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Unregulated input voltage IN(2)(3)(4) –0.3 45 V
Regulated output voltage OUT(2)(3) –0.3 7 V
Operating junction temperature range, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminal.
(3) Absolute negative voltage on these pins must not to go below –0.3 V.
(4) Absolute maximum voltage, withstands 45 V for 200 ms.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 Other pins ±500
Corner pins (4 pin: 1, 3, and 4;
5 pin: 1, 3, 4, and 5) 		±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Unregulated input voltage 4 40 V
VO Output voltage 0 5.5 V
CO Output capacitor requirements(1) 2.2 100 µF
ESRCO Output ESR requirements(2) 0.001 2 Ω
TJ Operating junction temperature range –40 150 °C
(1) The output capacitance range specified in this table is the effective value.
(2) Relevant ESR value at ƒ = 10 kHz.

7.4 Thermal Information

THERMAL METRIC(1)(2) DCY DBV UNIT
4 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 64.2 210.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46.8 126.1
RθJB Junction-to-board thermal resistance 13.3 38.4
ψJT Junction-to-top characterization parameter 6.3 16
ψJB Junction-to-board characterization parameter 13.2 37.5
(1) The thermal data is based on the JEDEC standard high-K profile, JESD 51-7, 2s2p four layer board with 2-oz copper. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated.
(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VIN = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 150 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VI Input voltage Fixed 2.5-V output, IO = 1 mA 4 40 V
Fixed 3.3-V output, IO = 1 mA 4 40
Fixed 5-V output, IO = 1 mA 5.5 40
IQ Quiescent current Fixed 2.5-V and 3.3-V version, VI = 4 to 40 V,
Fixed 5-V version, VI = 5.5 to 40 V, IO = 0.2 mA		 15 25 µA
VIN(UVLO) IN undervoltage detection Ramp VI up until the output turns on 3.65 V
Ramp VI down until the output turns OFF 3
REGULATED OUTPUT (OUT)
VO Regulated output Fixed 2.5-V version, VI = 4 to 40 V, IO = 1 to 150 mA –3% 3%
Fixed 3.3-V version, VI = 5 to 40 V, IO = 1 to 150 mA –3% 3%
Fixed 5-V version, VI = 6.5 to 40 V, IO = 1 to 150 mA –3% 3%
ΔVO(ΔVI) Line regulation VI = 6 to 40 V, ∆VO, IO = 10 mA 10 mV
ΔVO(ΔIL) Load regulation IO = 1 to 150 mA, ∆VO 20 mV
VDROP Dropout voltage Fixed 2.5-V version, VI – VO, IO = 50 mA 1.575 V
Fixed 2.5-V version, VI – VO, IO = 100 mA 1.575
Fixed 3.3-V version, VI – VO, IO = 50 mA 799 mV
Fixed 3.3-V version, VI – VO, IO = 100 mA 800
Fixed 5-V version, VI – VO, IO = 50 mA 220 400
Fixed 5-V version, VI – VO, IO = 100 mA 450 800
IO Output current VO in regulation 0 150 mA
IOCL Output current-limit OUT short to ground 150 500 mA
PSRR Power supply ripple rejection(1) Vrip = 0.5 Vpp, Load = 10 mA, ƒ = 100 Hz, CO = 2.2 µF 60 dB
OPERATING TEMPERATURE RANGE
Tsd Junction shutdown temperature 175 °C
Thys Hysteresis of thermal shutdown 25 °C
(1) Design Information—Not tested, ensured by characterization.

7.6 Typical Characteristics

D001_slvscj8.gif
Figure 1. 5-V Output Voltage vs Junction Temperature
D008_slvscj8.gif
VI = 14 V
Figure 3. 2.5-V Output Voltage vs Junction Temperature
D012_slvscj8.gif
IO = 0 mA
Figure 5. 3.3-V Output Voltage vs Supply Voltage
D003_slvscj8.gif
Figure 7. Quiescent Current vs Output Current
D004_slvscj8.gif
Figure 9. Dropout Voltage vs Output Current
D006_slvscj8.gif
IO = 10 mA VI = 14 V TA = 25°C
CO = 2.2 µF
Figure 11. Power Supply Rejection Ratio
waveform_load_100ma_slvscj8.gif
VI = 14 V CO = 2.2 µF 1 ms/div
VO = 5 V
Figure 13. Load Transient (1 to 100 mA, 5 V)
waveform_load_100ma_2p5V_slvscj8.gif
VI = 14 V CO = 2.2 µF 1 ms/div
VO = 2.5 V
Figure 15. Load Transient (1 to 100 mA, 2.5 V)
waveform_load_150ma_3p3V_slvscj8.gif
VI = 14 V CO = 2.2 µF 1 ms/div
VO = 3.3 V
Figure 17. Load Transient (1 to 150 mA, 3.3 V)
waveform_line_slvscj8.gif
VI = 9 to 16 V CO = 2.2 µF 1 ms/div
IO = 10 mA
Figure 19. Line Transient (VO = 5 V)
waveform_line_2p5v_slvscj8.gif
VI = 9 to 16 V CO = 2.2 µF 1 ms/div
IO = 10 mA
Figure 21. Line Transient (VO = 2.5 V)
waveform_powerup_3p3V_slvscj8.gif
CO = 2.2 µF, 400 µs/div
Figure 23. 3.3-V Power Up
D011_slvscj8.gif
VI = 14 V
Figure 2. 3.3-V Output Voltage vs Junction Temperature
D002_slvscj8.gif
IO = 0 mA
Figure 4. 5-V Output Voltage vs Supply Voltage
D009_slvscj8.gif
IO = 0 mA
Figure 6. 2.5-V Output Voltage vs Supply Voltage
D010_slvscj8.gif
IO = 0.2 mA
Figure 8. Quiescent Current vs Supply Voltage
D005_slvscj8.gif
IO = 100 mA VI = 14 V TA = 25°C
CO = 2.2 µF
Figure 10. Power Supply Rejection Ratio
D007_slvscj8.gif
Figure 12. ESR Stability vs Output Capacitance
waveform_load_100ma_3p3V_slvscj8.gif
VI = 14 V CO = 2.2 µF 1 ms/div
VO = 3.3 V
Figure 14. Load Transient (1 to 100 mA, 3.3 V)
waveform_load_150ma_slvscj8.gif
VI = 14 V CO = 2.2 µF 1 ms/div
VO = 5 V
Figure 16. Load Transient (1 to 150 mA, 5 V)
waveform_load_150ma_2p5V_slvscj8.gif
VI = 14 V CO = 2.2 µF 1 ms/div
VO = 2.5 V
Figure 18. Load Transient (1 to 150 mA, 2.5 V)
waveform_line_3p3v_slvscj8.gif
VI = 9 to 16 V CO = 2.2 µF 1 ms/div
IO = 10 mA
Figure 20. Line Transient (VO = 3.3 V)
waveform_powerup_slvscj8.gif
CO = 2.2 µF, 400 µs/div
Figure 22. 5-V Power Up
waveform_powerup_2p5V_slvscj8.gif
CO = 2.2 µF, 400 µs/div
Figure 24. 2.5-V Power Up