JAJSJ95C
June 2020 – August 2022
TPS7B86-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
Enable (EN)
7.3.2
Power-Good (PG)
7.3.3
Adjustable Power-Good Delay Timer (DELAY)
7.3.4
Undervoltage Lockout
7.3.5
Thermal Shutdown
7.3.6
Current Limit
7.4
Device Functional Modes
7.4.1
Device Functional Mode Comparison
7.4.2
Normal Operation
7.4.3
Dropout Operation
7.4.4
Disabled
8
Application and Implementation
8.1
Application Information
8.1.1
Input and Output Capacitor Selection
8.1.2
Adjustable Device Feedback Resistor Selection
8.1.3
Feed-Forward Capacitor
8.1.4
Dropout Voltage
8.1.5
Reverse Current
8.1.6
Power Dissipation (PD)
8.1.6.1
Thermal Performance Versus Copper Area
8.1.6.2
Power Dissipation Versus Ambient Temperature
8.1.7
Estimating Junction Temperature
8.1.8
Power-Good
8.1.8.1
Setting the Adjustable Power-Good Delay
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input Capacitor
8.2.2.2
Output Capacitor
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Package Mounting
8.4.1.2
Board Layout Recommendations to Improve PSRR and Noise Performance
8.4.2
Layout Examples
9
Device and Documentation Support
9.1
Device Support
9.1.1
Device Nomenclature
9.2
Receiving Notification of Documentation Updates
9.3
サポート・リソース
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDA|8
MPDS092F
KVU|5
MPSF019
サーマルパッド・メカニカル・データ
DDA|8
PPTD058I
KVU|5
QFND405
発注情報
jajsj95c_oa
jajsj95c_pm
8.2.2
Detailed Design Procedure