JAJSJ95C June   2020  – August 2022 TPS7B86-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Power-Good (PG)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Adjustable Device Feedback Resistor Selection
      3. 8.1.3 Feed-Forward Capacitor
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Thermal Performance Versus Copper Area
        2. 8.1.6.2 Power Dissipation Versus Ambient Temperature
      7. 8.1.7 Estimating Junction Temperature
      8. 8.1.8 Power-Good
        1. 8.1.8.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Package Mounting
        2. 8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 KVU Package,5-Pin TO-252(Top View)
GUID-5AD62F38-DD1F-4719-AC44-4C83D9086332-low.gifFigure 5-2 DDA Package (Without PG),
8-Pin HSOIC(Top View)
GUID-4B73DA9F-44D2-4DF9-85B9-EE452070170D-low.gifFigure 5-3 DDA Package (With PG),
8-Pin HSOIC, B Version(Top View)
Figure 5-4 DDA Package (With PG),
8-Pin HSOIC, D Version(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME KVU DDA (Without PG) DDA (B Version) DDA (D Version)
DELAY — — 3 3 O Power-good delay adjustment pin. Connect a capacitor from this pin to GND to set the PG reset delay. Leave this pin floating for a default (t(DLY_FIX)) delay. See the Section 7.3.2 section for more information. If this functionality is not desired, leave this pin floating because connecting this pin to GND causes a permanent increase in the GND current.
EN 2 7 7 6 I Enable pin. The device is disabled when the enable pin becomes lower than the enable logic input low level (VIL). Do not leave this pin floating because this pin is high impedance. If left floating, this pin may cause the device to enable or disable.
FB/NC 4 2 2 2 I This pin is a feedback pin when using an external resistor divider or an NC pin when using the device with a fixed output voltage. When using the adjustable device, this pin must be connected through a resistor divider to the output for the device to function. If using a fixed output this pin can either be left floating or connected to GND.
GND 3 5 5 4 G Ground pin. Connect this pin to the thermal pad with a low-impedance connection.
IN 1 8 8 8 P Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to GND as listed in the Section 6.3 table and the Section 8.2.2.1 section. Place the input capacitor as close to the input of the device as possible.
NC — 3, 4, 6 4 7 — No internal connection. This pin can be left floating or tied to GND for best thermal performance.
OUT 5 1 1 1 O Regulated output voltage pin. A capacitor is required from OUT to GND for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to GND; see the Section 6.3 table and the Section 8.2.2.2 section. Place the output capacitor as close to output of the device as possible. If using a high equivalent series resistance (ESR) capacitor, decouple the output with a 100-nF ceramic capacitor.
PG — — 6 5 O Active-high, power-good pin. An open-drain output indicates when the output voltage reaches VPG(TH,RISING) of the target. Using a feed-forward capacitor can disrupt PG (power good) functionality. See the Section 7.3.2 section for more information.
Thermal pad Pad Pad Pad Pad — Thermal pad. Connect the pad to GND for best possible thermal performance. See the Section 8.4 section for more information.