JAJSJ95C June   2020  – August 2022 TPS7B86-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Power-Good (PG)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Adjustable Device Feedback Resistor Selection
      3. 8.1.3 Feed-Forward Capacitor
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Thermal Performance Versus Copper Area
        2. 8.1.6.2 Power Dissipation Versus Ambient Temperature
      7. 8.1.7 Estimating Junction Temperature
      8. 8.1.8 Power-Good
        1. 8.1.8.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Package Mounting
        2. 8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

As depicted in Figure 8-11 and Figure 8-12, place the input and output capacitors close to the device for the layout of the TPS7B86-Q1. In order to enhance the thermal performance, place as many vias as possible around the device. These vias improve the heat transfer between the different GND planes in the PCB.

To improve AC performance such as PSRR, output noise, and transient response, use a board design with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.

Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability. Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. Do not use vias or long traces to connect the capacitors because may negatively affect system performance and even cause instability.

If possible, and to ensure the maximum performance specified in this document, use the same layout pattern used for the TPS7B86-Q1 evaluation board, available at www.ti.com.