JAJSJ95C June   2020  – August 2022 TPS7B86-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Power-Good (PG)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Adjustable Device Feedback Resistor Selection
      3. 8.1.3 Feed-Forward Capacitor
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Thermal Performance Versus Copper Area
        2. 8.1.6.2 Power Dissipation Versus Ambient Temperature
      7. 8.1.7 Estimating Junction Temperature
      8. 8.1.8 Power-Good
        1. 8.1.8.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Package Mounting
        2. 8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.6.1 Thermal Performance Versus Copper Area

The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Section 6.4 table is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.

GUID-2BF2C0B9-4F00-41EC-AD78-3CA4192C654F-low.gifFigure 8-1 JEDEC Standard 2s2p PCB

Figure 8-2 through Figure 8-5 illustrate the functions of RθJA and ψJB versus copper area and thickness. These plots are generated with a 101.6-mm × 101.6-mm × 1.6-mm PCB of two and four layers. For the 4-layer board, inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A 2x3 (DDA package) or a 3×4 (KVU package) array of thermal vias with a 300-µm drill diameter and 25-µm copper plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.

GUID-20201130-CA0I-JXZ9-VQBB-ZLGZJQHRDMXL-low.gifFigure 8-2 RθJA vs Copper Area (DDA Package)
GUID-20201130-CA0I-KJZJ-CKKS-C4P8SCJXLBHP-low.gifFigure 8-4 RθJA vs Copper Area (KVU Package)
GUID-20201130-CA0I-VKGL-ZWR5-K0NZZNWKFNXK-low.gifFigure 8-3 ψJB vs Copper Area (DDA Package)
GUID-20201130-CA0I-23XD-VJ0L-KQLZR1BXC847-low.gifFigure 8-5 ψJB vs Copper Area (KVU Package)