JAJSJ95C June   2020  – August 2022 TPS7B86-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Power-Good (PG)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Adjustable Device Feedback Resistor Selection
      3. 8.1.3 Feed-Forward Capacitor
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Thermal Performance Versus Copper Area
        2. 8.1.6.2 Power Dissipation Versus Ambient Temperature
      7. 8.1.7 Estimating Junction Temperature
      8. 8.1.8 Power-Good
        1. 8.1.8.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Package Mounting
        2. 8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

specified at TJ = –40°C to +150°C, VIN = 13.5 V,  IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω,  CIN = 1 µF, and VEN = 2 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER Test Conditions MIN TYP MAX UNIT
VOUT Regulated output (DDA package) VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ = 25ºC(1) –0.75 0.75 %
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ = 25ºC(1) –0.75 0.75
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA(1) –0.85 0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1) –0.85 0.85
VOUT Regulated output (KVU Package) VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ = 25ºC(1) –0.85 0.85 %
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ = 25ºC(1) –0.85 0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA(1) –1.15 1.15
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1) –1.15 1.15
ΔVOUT(ΔIOUT) Load regulation (B Version) VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3 V 0.45 %
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3 V 0.475 %
ΔVOUT(ΔIOUT) Load regulation VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3 V 0.425 %
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3 V 0.45
ΔVOUT(ΔIOUT) Load regulation (adjustable output only) VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT < 3.3 V 0.625 %
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT < 3.3 V 0.65
ΔVOUT(ΔVIN) Line regulation VIN = VOUT + 1 V to 40 V,  IOUT = 100 µA 0.2 %
ΔVOUT Load transient response settling time(3) tR = tF = 1 µs; COUT = 10 µF, VOUT ≥ 3.3V 100 µs
ΔVOUT Load transient response overshoot, undershoot(2) tR = tF = 1 µs; COUT = 10 µF, VOUT ≥ 3.3V IOUT = 150 mA to 350 mA –2% %VOUT
IOUT = 350 mA to 150 mA 10%
IOUT = 0 mA to 500 mA –10%
ΔVOUT Load transient response overshoot, undershoot(2) tR = tF = 1 µs; COUT = 10 µF, VOUT < 3.3V IOUT = 150 mA to 350 mA –2.5% %VOUT
IOUT = 350 mA to 150 mA 10%
IOUT = 0 mA to 500 mA –10%
IQ Quiescent current VIN = VOUT + 1 V to 40V, IOUT = 0 mA, TJ = 25ºC(3) 17 21 µA
VIN = VOUT + 1 V to 40 V, IOUT = 0 mA(3) 26
IOUT = 500 µA 35
ISHUTDOWN Shutdown supply current (IGND) VEN = 0 V, TJ = 25ºC 2.5 µA
VEN = 0 V 4
VDO Dropout voltage fixed output voltages (DDA Package) IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95 43 mV
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 260 360
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 335 475
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 360 535
VDO Dropout voltage adjustable output IOUT ≤ 1 mA, VFB = 0.61 V, VIN = 3 V 43 mV
IOUT = 315 mA, VFB = 0.61 V, VIN = 3 V 400
IOUT = 450 mA, VFB = 0.61 V, VIN = 3 V 525
IOUT = 500 mA, VFB = 0.61 V, VIN = 3 V 570
VDO Dropout voltage fixed output voltages (KVU Package) IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95 46 mV
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 275 400
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 360 525
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 390 575
VDO Dropout voltage adjustable output voltages (KVU Package) IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95 46 mV
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 327 440 mV
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 428 575 mV
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 464 630 mV
VFB Feedback voltage Reference voltage for FB 0.644 0.65 0.656 V
IFB Feedback current Current into FB pin -10 10 nA
IEN EN pin current VEN = VIN = 13.5 V 50 nA
VUVLO(RISING) Rising input supply UVLO VIN rising 2.6 2.7 2.82 V
VUVLO(FALLING) Falling input supply UVLO VIN falling 2.38 2.5 2.6 V
VUVLO(HYST) V UVLO(IN) hysteresis 230 mV
VIL Enable logic input low level 0.7 V
VIH Enable logic input high level 2 V
ICL Output current limit VIN = VOUT + 1 V, VOUT short to 90% x VOUT(NOM) 540 780 mA
PSRR Power supply rejection ratio VIN - VOUT = 1 V, frequency = 1 kHz, IOUT = 450 mA 70 dB
VPG(OL) PG pin low level output voltage VOUT ≤ 0.83 x VOUT 0.4 V
VPG(TH,RISING) Default power-good threshold VOUT rising 85 95 %VOUT
VPG(TH,FALLING) Default power-good threshold VOUT falling 83 93
VPG(HYST) Power-good hysteresis 2
VDLY(TH) Threshold to release power-good high Voltage at DELAY pin rising 1.17 1.21 1.25 V
IDLY(CHARGE) Delay capacitor charging current Voltage at DELAY pin = 1 V 1 1.5 2 µA
TJ Junction temperature –40 150 °C
TSD(SHUTDOWN) Junction shutdown temperature 175 °C
TSD(HYST) Hysteresis of thermal shutdown 20 °C
(1) Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal operation. See the thermal dissipation section for more information on how much power the device can dissipate while maintaining a junction temperature below 150℃.
(2) Specified by design.
(3) For the adjustable output this is tested in unity gain and resistor current is not included.