JAJSKF7A December   2020  – April 2021 TPS7B87-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good (PG)
      2. 7.3.2 Adjustable Power-Good Delay Timer (DELAY)
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Pulling Up the PG Pin to a Different Voltage
      7. 8.1.7 Power-Good
        1. 8.1.7.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 KVU Package,5-Pin TO-252,Top View
GUID-20201202-CA0I-N1F3-TPDP-K5NBWTDW3H5G-low.gifFigure 5-2 DDA Package,8-Pin HSOIC,Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME KVU DDA
DELAY 4 3 I Power-good delay adjustment pin. Connect a capacitor from this pin to GND to set the PG reset delay. Leave this pin floating for a default (t(DLY_FIX)) delay. See the Section 7.3.1 section for more information. If this functionality is not desired, leave this pin floating because connecting this pin to GND causes a permanent increase in the GND current.
GND 3 5 G Ground reference
NC — 2, 4, 7 — No internal connection. This pin can be left floating or tied to GND for best thermal performance.
PG 2 6 I Power-good pin. This pin has an internal pullup resistor. Do not connect this pin to VOUT or any other biased voltage rail. VPG is logic level high when VOUT is above the power-good threshold. See the Section 7.3.1 section for more information.
IN 1 8 P Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to GND as listed in the Recommended Operating Conditions table and the Section 8.2.2.1 section. Place the input capacitor as close to the input of the device as possible.
OUT 5 1 O Regulated output voltage pin. A capacitor is required from OUT to GND for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to GND; see the Recommended Operating Conditions table and the Section 8.2.2.2 section. Place the output capacitor as close to output of the device as possible. If using a high equivalent series resistance (ESR) capacitor, decouple the output with a 100-nF ceramic capacitor.
Thermal pad Pad Pad — Connect the thermal pad to a large area GND plane for improved thermal performance.
(1) I = input; O = output; P = power; G = ground.