JAJSKF7A December   2020  – April 2021 TPS7B87-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good (PG)
      2. 7.3.2 Adjustable Power-Good Delay Timer (DELAY)
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Pulling Up the PG Pin to a Different Voltage
      7. 8.1.7 Power-Good
        1. 8.1.7.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.4.2 Power Dissipation Versus Ambient Temperature

Figure 8-6 is based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation was estimated using the following equation. As discussed in the An empirical analysis of the impact of board layout on LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%.

Equation 4. GUID-20201021-CA0I-QC5G-DT5Q-9CXMF9K2QPZJ-low.gif
GUID-20201124-CA0I-KKSD-9VBP-NG63HFP0SKLD-low.gif Figure 8-6 TPS7B87-Q1 Allowable Power Dissipation