TPS7H1101A-SP 1.5V～7V入力、3A、放射線強化型LDOレギュレータ
- JAJSD99A April 2017 – August 2017 TPS7H1101A-SP
  
  PRODUCTION DATA.

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TPS7H1101A-SP 1.5V～7V入力、3A、放射線強化型LDOレギュレータ

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

5962R13202:
- 放射線強度保証(RHA): 最大TID 100krad (Si)
- 総照射線量耐性: 100krad (Si)
- ELDRSフリー: 100krad (Si)
- 線量率: 10mrad (Si)/s
- 単一イベント・ラッチアップ(SEL)耐性:
  LET = 85 MeV-cm²/mg
- SEBおよびSEGR耐性:
  LET = 85 MeV-cm²/mg
- SET/SEFI開始スレッショルド > 40 MeV-cm²/mg、詳細については「放射線レポート」(SNAA257)を参照
  - 下流の重要なコンポーネントの損傷を防止するため、常にLOWにアップセットするよう設計
- SET/SEFIクロスセクション・プロット、詳細については「放射線レポート」(SNAA257)を参照
非常に低いV_IN範囲: 1.5V～7V
最大出力電流 3A
電流共有/並列動作により、最大6Aの出力電流を供給可能
セラミック出力コンデンサで安定動作
ライン、負荷、温度の範囲全体にわたって±2%の精度
外付けのコンデンサによりソフトスタートをプログラム可能
すべての入力電圧にわたる入力イネーブルとパワー・グッド出力によるパワー・シーケンス
非常に低いドロップアウトLDO電圧:
1A (25℃)、V_OUT = 1.8Vにおいて62mV
低ノイズ:
V_IN = 2V、V_OUT = 1.8V、3A時に20.33µVRMS
PSRR: 1kHzにおいて45dB超
非常に優れた負荷/ライン過渡応答
フォールドバック電流制限
「ツールとソフトウェア」タブを参照
熱的に強化されたCFPパッケージ(0.6℃/W R_θJC)

2 アプリケーション

人工衛星のポイント・オブ・ロード電源: FPGA、マイクロコントローラ、ASIC、データ・コンバータ用
人工衛星のペイロード
RF、VCO、受信機、アンプ用の、放射線強化された低ノイズのリニア・レギュレータ電源
クリーンなアナログ電源要件
軍用温度範囲(-55℃～125℃)で利用可能
エンジニアリング評価(/EM)サンプルを利用可能⁽¹⁾

3 概要

TPS7H1101A-SPはTPS7H1101-SPの改良版で、入力電圧範囲の全体にわたってイネーブル機能を使用できます。放射線強化されたLDOリニア・レギュレータであり、PMOSパス素子構成を使用します。1.5V～7Vの広い入力電圧範囲で動作し、非常に優れたPSRRを実現しています。TPS7H1101A-SPには、正確でプログラム可能、かつ非常に広い範囲で調整可能な、フォールドバック電流制限が実装されています。FPGA、DSP、マイクロコントローラの複雑な電力要件に対応するため、TPS7H1101A-SPにはイネーブル・オンおよびオフ機能、ソフトスタートのプログラム機能、電流共有機能、パワー・グッドのオープン・ドレイン出力が搭載されています。

製品情報⁽²⁾

型番	パッケージ	本体サイズ(公称)
TPS7H1101A-SP	CFP (16)	11.00mm×9.60mm
TPS7H1101A-SP	KGD	—

これらのユニットは、技術的な評価のみを目的としています。標準とは異なるフロー(バーンインがないなど)に従って処理されており、25℃の温度定格のみがテストされれています。これらのユニットは、認定、量産、放射線テスト、航空での使用には適していません。これらの部品は、MILに規定されている温度範囲-55℃～125℃、または動作寿命全体にわたる性能を保証されていません。
提供されているすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。

代表的なアプリケーション回路

4 改訂履歴

Changes from * Revision (April 2017) to A Revision

Added Bare Die Information tableGo
Added Bond Pad Coordinates in Microns tableGo

5 Pin Configuration and Functions

HKR Package

16-Pin CFP

Bottom View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
SS	1	I/O	Soft-start terminal. Connecting an external capacitor slows down the output voltage ramp rate after enable event.
EN	2	I	Enable terminal. Driving this terminal to logic high enables the device; driving the terminal to logic low disables the device.
V_IN	3	I	Unregulated supply voltage. TI recommends to connect an input capacitor as a good analog circuit practice.
	4
	5
	6
PCL	7	I/O	Programmable current limit. A resistor to GND sets the overcurrent limit activation point. The range of resistor that can be used on the PCL terminal to GND is 8.2 kΩ to 160 kΩ.
GND	8	—	Ground/thermal pad.⁽¹⁾
PG/OC	9	O	Power Good terminal. PG is an open-drain output to indicate the output voltage reaches 90% of target. PG terminal is also used as indicator when an overcurrent condition is activated. PG pin should have a pull-up resistor to the V_OUT pin.
CS	10	I/O	Current sense terminal. Resistor connected from CS to V_IN. CS terminal indicates voltage proportional to output current. CS terminal low: Foldback current limit disabled. CS terminal high: Foldback current limit enabled.
V_OUT	11	O	Regulated output.
	12
	13
	14
COMP	15	I/O	Internal compensation point for error amplifier.
FB	16	I	The output voltage feedback input through voltage dividers. See the Adjustable Output Voltage (Feedback Circuit) section.

(1) Thermal pad must be connected to GND.

Bare Die Information

DIE THICKNESS	BACKSIDE FINISH	BACKSIDE POTENTIAL	BOND PAD METALLIZATION COMPOSITION	BOND PAD THICKNESS
15 mils	Silicon with backgrind	Ground	AlCu	30 kA

NOTE:

All dimensions are in microns.

Bond Pad Coordinates in Microns

DESCRIPTION	PAD NUMBER	X MIN	Y MIN	X MAX	Y MAX
SS	1	109.89	4046.805	287.19	4224.105
EN	2	109.89	3493.35	287.19	3670.65
VIN	3	1359.99	3021.345	1537.29	3198.645
VIN	4	1359.99	2749.005	1537.29	2926.305
VIN	5	1359.99	2553.705	1537.29	2731.005
VIN	6	1359.99	2281.365	1537.29	2458.665
VIN	7	1359.99	2086.065	1537.29	2263.365
VIN	8	1359.99	1813.725	1537.29	1991.025
VIN	9	1359.99	1618.425	1537.29	1795.725
PCL	10	109.89	660.285	287.19	837.585
GND	11	109.89	319.455	287.19	496.755
GND	12	392.58	109.935	569.88	287.235
VIN	13	1359.99	1346.085	1537.29	1523.385
PG/OC	14	2898.945	379.62	3076.245	556.92
CS	15	2898.945	724.32	3076.245	901.62
VOUT	16	2829.105	1384.695	3006.405	1561.995
VOUT	17	2829.105	1579.815	3006.405	1757.115
VOUT	18	2829.105	1852.335	3006.405	2029.635
VOUT	19	2829.105	2047.455	3006.405	2224.755
VOUT	20	2829.105	2319.975	3006.405	2497.275
VOUT	21	2829.105	2515.095	3006.405	2692.395
VOUT	22	2829.105	2787.615	3006.405	2964.915
VOUT	23	2829.105	2982.735	3006.405	3160.035
COMP	24	2898.945	3519.72	3076.245	3697.02
FB	25	2898.945	3956.535	3076.245	4133.835

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage	V_IN, PG	–0.3	7.5	V
Input voltage	FB, COMP, PCL, CS, EN	–0.3	V_IN + 0.3	V
Output voltage	V_OUT, SS	–0.3	7.5	V
PG terminal sink current		0.001	5	mA
Maximum operating junction temperature, T_J		–55	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
T_J	Operating junction temperature		–55		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS7H1101A-SP	UNIT
		HKR (CFP)
		16 PINS
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.6	°C/W

(1) Do not allow package body temperature to exceed 265°C at any time or permanent damage may result.

(2) Maximum power dissipation may be limited by overcurrent protection.

6.5 Electrical Characteristics

1.5 V ≤ V_IN ≤ 7 V, V_OUT(target) = V_IN – 0.35 V, I_OUT = 10 mA, V_EN = 1.1 V, C_OUT = 22 µF, PG terminal pulled up to V_IN with 50 kΩ, over operating temperature range (T_J = –55°C to 125°C), unless otherwise noted. Typical values are at T_J = 25°C.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IN	Input voltage range			1.5		7	V
V_FB	Feedback terminal voltage⁽²⁾	0 A ≤ I_OUT ≤ 3 A, 1.5 V ≤ V_IN ≤ 7 V		0.594	0.605	0.616	V
V_OUT	Output voltage range			0.8		V_IN	V
	Output voltage accuracy⁽²⁾	0 A ≤ I_OUT ≤ 3 A, 1.5 V ≤ V_IN ≤ 7 V, V_OUT = 0.8 V, 1.2 V, 1.8 V, 6.65 V		–2%		2%
ΔV_OUT%/ ΔV_IN	Line regulation	1.5 V ≤ V_IN ≤ 7 V		–0.07	0.01	0.07	%/V
ΔV_OUT%/ ΔI_OUT	Load regulation	0.8 V ≤ V_OUT ≤ 6.65 V, 0 ≤ I_Load ≤ 3 A			0.08		%/A
ΔV_OUT	DC input line regulation	1.5 V ≤ V_IN ≤ 7 V, V_OUT = 0.8 V, 1.2 V, 1.8 V, I_OUT = 10 mA, T_J = –55°C⁽¹⁾			0.5	3	mV
		1.5 V ≤ V_IN ≤ 7 V, V_OUT = 0.8 V, 1.2 V, 1.8 V, I_OUT = 10 mA, T_J = 25°C⁽¹⁾			0.2	0.6
		1.5 V ≤ V_IN ≤ 7 V, V_OUT = 0.8 V, 1.2 V, 1.8 V, I_OUT = 10 mA, T_J = 125°C⁽¹⁾			0.2	1
ΔV_O	DC output load regulation⁽³⁾	V_OUT = 0.8 V, 0 ≤ I_Load ≤ 1 A, T_J = –55°C⁽¹⁾			0.4	1	mV
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 1 A, T_J = 25°C⁽¹⁾			0.6	1.1
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 1 A, T_J = 125°C⁽¹⁾			0.8	1.3
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 2 A, T_J = –55°C⁽¹⁾			0.8	1.8
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 2 A, T_J = 25°C⁽¹⁾			1.3	1.8
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 2 A, T_J = 125°C⁽¹⁾			1.6	2.4
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 3 A, T_J = –55°C⁽¹⁾			1.1	1.9
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 3 A, T_J = 25°C⁽¹⁾			1.9	2.6
		V_OUT = 0.8 V, 0 ≤ I_Load ≤ 3 A, T_J = 125°C⁽¹⁾			2.5	3.4
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 1 A, T_J = –55°C⁽¹⁾			0.3	1.2
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 1 A, T_J = 25°C⁽¹⁾			0.5	1.3
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 1 A, T_J = 125°C⁽¹⁾			0.6	1.3
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 2 A, T_J = –55°C⁽¹⁾			0.8	1.6
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 2 A, T_J = 25°C⁽¹⁾			1.1	2.1
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 2 A, T_J = 125°C⁽¹⁾			1.5	2.1
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 3 A, T_J = –55°C⁽¹⁾			1	1.7
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 3 A, T_J = 25°C⁽¹⁾			1.1	2.4
		V_OUT = 1.2 V, 0 ≤ I_Load ≤ 3 A, T_J = 125°C⁽¹⁾			2.2	3.5
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 1 A, T_J = –55°C⁽¹⁾			0.1	0.9
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 1 A, T_J = 25°C⁽¹⁾			0.3	0.9
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 1 A, T_J = 125°C⁽¹⁾			0.4	1.2
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 2 A, T_J = –55°C⁽¹⁾			1.4	2.4
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 2 A, T_J = 25°C⁽¹⁾			0.7	1.4
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 2 A, T_J = 125°C⁽¹⁾			0.6	1.9
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 3 A, T_J = –55°C⁽¹⁾			2.5	3.9
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 3 A, T_J = 25°C⁽¹⁾			1.2	2.1
		V_OUT = 1.8 V, 0 ≤ I_Load ≤ 3 A, T_J = 125°C⁽¹⁾			1.2	2.5
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 1 A, T_J = –55°C⁽¹⁾			1.5	2.9
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 1 A, T_J = 25°C⁽¹⁾			0.4	2.6
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 1 A, T_J = 125°C⁽¹⁾			2.8	3.5
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 2 A, T_J = –55°C⁽¹⁾			3.5	5.9
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 2 A, T_J = 25°C⁽¹⁾			1.1	4.7
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 2 A, T_J = 125°C⁽¹⁾			5.8	8
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 3 A, T_J = –55°C⁽¹⁾			5.6	9.3
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 3 A, T_J = 25°C⁽¹⁾			3.7	8
		V_OUT = 6.65 V, 0 ≤ I_Load ≤ 3 A, T_J = 125°C⁽¹⁾			13	25
V_DO	Dropout voltage⁽³⁾	I_OUT = 3 A, V_OUT = 1.3 V, V_IN = V_OUT + V_DO			210	335	mV
I_CL	Programmable output current limit range	V_IN = 1.5 V, V_OUT = 1.2 V, PCL resistance = 47 kΩ		500		750	mA
I_CL	Programmable output current limit range	V_IN = 1.5 V, V_OUT = 1.2 V, PCL resistance varies		200		3500⁽⁵⁾	mA
V_CS	Operating voltage range at CS			0.3		V_IN	V
CSR	Current sense ratio	I_LOAD / I_CS, V_IN = 2.3 V, V_OUT = 1.9 V		47394	47500	56000	A/A
I_GND	GND terminal current	V_IN = 1.5 V, V_OUT = 1.2 V, I_OUT = 2 A			10	16	mA
I_Q	Quiescent current (no load)	V_IN = V_OUT + 0.5 V, I_OUT = 0 A			7	10	mA
I_SHDN	Shutdown current	1.5 V ≤ V_IN ≤ 7 V, pre and post 100 krads (Si), T_J = 25°C⁽⁴⁾			26	230	µA
I_SNS, I_FB	FB/SNS terminal current	V_IN = 7 V, V_OUT = 6.65 V			1	5	nA
I_EN	EN terminal input current	V_IN = 7 V, V_EN = 7 V, V_OUT = 6.65 V			20	150	nA
V_ILEN	EN terminal input low (disable)	1.5 V < V_IN < 7 V				0.55	V
V_IHEN	EN terminal input high (enable)	1.5 V < V_IN < 7 V		V_IN – 0.7			V
Eprop Dly	Enable terminal propagation delay	V_IN = 2.2 V, EN rise to I_OUTrise			650	1000	µs
T_EN	Enable terminal turn-on delay	V_IN = 2.2 V, V_OUT = 1.8 V, I_LOAD = 1 A, C_OUT = 220 µF, C_SS = 2 nF			1.4	1.6	ms
V_THPG	PG threshold	No load, 0.8 V ≤ V_OUT ≤ 6.65 V		86%	90%
V_THPGHYS	PG hysteresis	1.5 V ≤ V_IN ≤ 7 V			2%
V_OL_PG	PG terminal output low	I_PG = 0 mA to –1 mA			120	300	mV
I_LKGPG	PG terminal leakage current	V_OUT > V_THPG, V_PG = 1.2 V			0.2	1.5	µA
I_LKGPG	PG terminal leakage current	V_OUT > V_THPG, V_PG = 7 V			0.5	2.5	µA
I_SS	SS terminal charge current	V_IN = 1.5 V to 7 V			2.5	3.5	µA
I_SSdisb	SS terminal disable current	V_IN = 1.5 V to 7 V			5	10	µA
V_SS	SS terminal voltage (device enabled)⁽⁶⁾	V_IN = 1.5 V to 7 V				1.232	V
V_SSdisb	SS terminal low-level input voltage to disable device	V_IN = 1.5 V to 7 V				0.4	V
PSRR	Power-supply rejection ratio	V_IN = 2.5 V, V_OUT = 1.8 V, C_OUT = 220 µF	1 kHz		48		dB
PSRR	Power-supply rejection ratio	V_IN = 2.5 V, V_OUT = 1.8 V, C_OUT = 220 µF	100 kHz		25		dB
V_N	Output noise voltage	BW = 10 Hz to 100 kHz, I_OUT = 3 A, V_IN = 2 V, V_OUT = 1.8 V			20.33		µV_RMS
TSD	Thermal shutdown temperature				185		°C

(1) Line and load regulations done under pulse condition for t < 10 ms.

(2) The output voltage accuracy of condition at I_OUT = 2 A and I_OUT = 3 A is specified by characterization, but not production tested.

(3) The parameter is specified to the limit in characterization, but not production tested.

(4) This maximum limit applies to SMD 5962R13202 post 100-krads (Si) test at 25°C.

(5) The maximum limit of the I_CLparameter is specified to the limit in characterization, but not production tested.

(6) Any external pullup voltage should not exceed 1.188 V.

6.6 Typical Characteristics

Figure 1. Feedback Voltage vs Temperature

Figure 3. Ground Current vs Temperature

Figure 5. Shutdown Current vs Temperature

V_IN = 2.5 V	V_OUT = 1.8 V

Figure 7. Power Supply Ripple Rejection vs Frequency

Figure 2. Quiescent Current vs Temperature

V_OUT = 1.8 V	Load = 3 A

Figure 4. Dropout Voltage vs Temperature

Figure 6. PG Threshold vs Temperature

7 Detailed Description

7.1 Overview

The TPS7H1101A-SP is 3-A, 1.5-V to 7-V LDO linear regulator that uses PMOS pass element configuration.

It uses TI’s proprietary process to achieve low noise, high PSRR combined with high-thermal performance in a 16-pin ceramic flatpack package (HKR).

A number of features are incorporated in the design to provide high reliability and system flexibility. Current foldback, current limit, and thermal protection are incorporated in the design to make it viable for harsh environments.

The device also has a current sense monitoring feature. A resistor connected from the current sense (CS) terminal to VIN indicates voltage proportional to the output current. When CS is held high, foldback current limit is enabled. Shorting CS low disables the foldback current limit.

A resistor connected from the programmable current limit (PCL) terminal to ground sets the overcurrent limit activation point. When overcurrent limit activation point is reached, it results in LDO going into current foldback mode. Output current is reduced to approximately 50% of the current limit set point. The PCL section provides a detailed description of this feature.

TPS7H1101A-SP incorporates thermal protection, which disables the output when the junction temperature rises approximately 185°C, allowing the device to cool. Cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.

A resistor connected from the CS terminal to VIN indicates voltage proportional to the output load current.

To provide system flexibility for demanding current needs, the LDO can be configured in parallel operation as indicated in Figure 20. The Current Sharing section provides detailed parallel operation information.

An enable feature is incorporated in the design allowing the user to enable or disable the LDO. Power Good, an open-drain connection, indicates the status of the output voltage. These provide the customers system flexibility in monitoring and controlling the LDO operation.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Soft Start

Connecting a capacitor from the SS terminal to GND (C_SS) slows down the output voltage ramp rate. The soft-start capacitor charges up to 1.2 V.

Equation 1. TPS7H1101A-SP eq3_css_slvsas4.gif

where

t_ss = soft-start time
I_ss = 2.5 µA
V_FB = V_REF/ 2 = 0.605 V

7.3.2 Power Good (PG)

Power Good terminal (9) is an open-drain connection and can be used to sequence multiple LDOs. Figure 8 shows typical connection. The PG terminal will be pulled low until the output voltage reaches 90% of its maximum level. At that point, the PG pin will be pulled up. Since the PG pin is open drain, it can be pulled up to any voltage as long as it does not exceed the absolute max of 7.5 V listed in the Electrical Characteristics table.

Figure 8. Sequencing LDOs with Power Good

NOTE

For PSpice models, WEBENCH, and mini-POL reference design, see the Tools & Software tab.

PSpice average model (stability – Bode plot)
PSpice transient model (switching waveforms)
WEBENCH design tool, www.ti.com/product/TPS7H1101A-SP/toolssoftware

7.4 Device Functional Modes

7.4.1 Enable/Disable

For V_IN from 1.5 V to 7 V, TPS7H1101A-SP can be disabled by pulling the enable terminal to logic low at a minimum of 0.7 V. In all cases, the enable terminal should be connected to V_IN.