SLVSH48A May   2024  – September 2024 TPS7H1121-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspections
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Output Voltage (Feedback Circuit)
      2. 8.3.2  Enable
      3. 8.3.3  Dropout Voltage VDO
      4. 8.3.4  Output Voltage Accuracy
      5. 8.3.5  Output Noise
      6. 8.3.6  Power Supply Rejection Ratio (PSRR)
      7. 8.3.7  Soft Start
      8. 8.3.8  Power Good (PG)
      9. 8.3.9  Stability
        1. 8.3.9.1 Stability
        2. 8.3.9.2 STAB Pin
      10. 8.3.10 Programmable Current Limit
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable / Disable
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Configuration
        2. 9.2.2.2 Output Voltage Accuracy
        3. 9.2.2.3 Enable Threshold
        4. 9.2.2.4 Soft Start Capacitor
        5. 9.2.2.5 Programmable Current Limit Resistor
        6. 9.2.2.6 Characterization of Overcurrent Events that Exceed Thermal Limits
        7. 9.2.2.7 Power Good Pull Up Resistor
        8. 9.2.2.8 Capacitors
          1. 9.2.2.8.1 Hybrid Output Capacitor Network
        9. 9.2.2.9 Frequency Compensation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HFT|22
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over 2.25V ≤ VIN ≤ 14V, VOUT(set) ≤ VIN – 0.5V,  IOUT = 10mA, COUT = 47µF, over operating temperature range (TA = – 55°C to 125°C), typical values are at TA = 25°C, unless otherwise noted; includes RLAT at TA = 25°C  if sub-group number is present for QML RHA and SEP devices(2)
PARAMETER Test Conditions SUB-
GROUP(1)		 MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
VDO Dropout voltage,
see Figure 7-1		 VOUT(set) = 2.25V
VOUT(measured) = 98% × VOUT(NOM)		 IOUT = 100mA 1,2,3 28 60 mV
IOUT = 250mA 1,2,3 70 141
IOUT = 500mA 1,2,3 150 280
IOUT = 1A
1,2,3

 300 570
VOUT(set) = 2.5V
VOUT(measured) = 98% × VOUT(NOM)		 IOUT = 1.5A
1,2,3

 525 750
IOUT = 2A 
1,2,3

 570 900
3V ≤ VOUT(set) ≤ 13.3V
VOUT(measured) = 98% × VOUT(NOM)		 IOUT = 100mA
1,2,3

 20 50
IOUT = 250mA
1,2,3

 70 100
IOUT = 500mA
1,2,3

 125 180
IOUT = 1A
1,2,3

 300 340
IOUT = 1.5A
1,2,3

 325 490
IOUT = 2A 
1,2,3

 500 700

IPCL
 		 Programmed current limit VIN = 3.3V,
VOUT(short) = 0.1V		 RCL = 442kΩ 1,2,3 0.19 0.320 0.45 A
RCL = 174kΩ
1,2,3

 0.485 0.75 1.01
RCL = 82.5kΩ
1,2,3

 1.16 1.55 1.94
RCL = 41.2kΩ
1,2,3

 2.4 3 3.6
IQ Quiescent current VEN = 7V, IOUT = 0A
1,2,3

 8.75 15 mA
IGND
(IIN - IOUT)		 Ground current VEN = 7V IOUT = 1A
1,2,3

 10 18 mA
IOUT = 2A
1,2,3

 13 20
VLDO Internal linear regulator output voltage VIN = 2.25V
1,2,3

 2.05 2.2 2.25 V
3V ≤ VIN ≤ 14V
1,2,3

 2.30 2.55 2.78
ISHDN Shutdown current VEN = 0V, IOUT = 0A, VOUT = 0V
1,2,3

 380 775 µA
IFB Feedback leakage current VFB = 0.7V
1,2,3

 1 15 nA
ACCURACY
VACC Output voltage accuracy 10mA ≤ IOUT ≤ 2A,
0.6V ≤ VOUT ≤ VIN – VDO,
PD ≤ 3W(3)		 3V ≤ VIN ≤ 14V 1,2,3 –1.5% 1.5%
3V ≤ VIN ≤ 14V
TA = 25°C		 1 –1.1% 1.1%

2.25V ≤ VIN ≤ 3V

 1,2,3 -1.8% 1.8%
VFB Feedback voltage 3V ≤ VIN ≤ 14V 1,2,3 0.588 0.596 0.606 V
TA = 25°C 1 0.591 0.596 0.603
2.25V ≤ VIN ≤ 3V 1,2,3 0.586 0.596 0.608
ΔVOUT/ ΔVIN Line regulation,
see Figure 7-2		 3V ≤ VIN ≤ 14V 1,2,3 100 650 µV/V
2.25V ≤ VIN ≤ 3V 1,2,3 285 1800
ΔVOUT/ ΔIOUT Load Regulation, 
see Figure 7-3		 10mA ≤ IOUT ≤ 2A, VIN  = 5V, VOUT = 3.3V 1,2,3 4 16 mV/A
ENABLE
VEN(rising) Enable rising threshold (turn-on) 1,2,3 0.565 0.605 0.625 V
VEN(falling) Enable falling threshold (turn-off) 1,2,3 0.465 0.5 0.52 V
tEN(delay) EN propagation delay EN high to VOUT = 10mV 9,10,11 50 150 µs
IEN(LKG) Enable leakage current VEN = 7V 1,2,3 1 30 nA
TSD Thermal shutdown enter temperature 160 °C
TSD Thermal shutdown exit temperature 130 °C
POWER GOOD
VPG_RISE Power good rising as percent of VOUT 1,2,3 93% 95% 97%
VPG_FALL Power good falling as percent of VOUT 1,2,3 88.5% 91.5% 94%
VPG(OL) Power good output low IPG(SINK) = 2mA 1,2,3 90 190 mV
VIN(MIN_PG) Minimum VIN for valid PG (VPG < 0.5V) IPG(SINK) = 0.5mA 1,2,3 0.6 0.8 V
IPG(LKG) Power good leakage VPG = 7V, VFB = 0.7V 1,2,3 0.05 2 µA
SOFT START
ISS Soft-start current 1,2,3 1.4 2 2.7 µA
tSS Soft-start time VIN = 5V, VOUT = 3.3V, measured from VOUT = 10mV to PG assert CSS = 1nF
9,10,11

 0.22 0.35 0.48 ms
CSS = 33nF
9,10,11

 5.5 10 14.5
STABILITY
GM Gain Margin VIN = 5V, VOUT = 3.3V, IOUT  = 1A,
COUT = 47µF,  TA = 25℃,
No External Compensation		 24 dB
PM Phase Margin 60°
NOISE AND PSRR
PSRR Power-supply rejection ratio VIN = 5V, VOUT = 3.3V, IOUT = 1A, CSS = 5.6nF fripple = 100Hz 68 dB
fripple = 1kHz 72
fripple = 10kHz 51
fripple = 100kHz 40
fripple = 1MHz 34
VN Output noise voltage 
(bandwidth from 10Hz to 100kHz)		 VIN = 5V, VOUT = 3.3V, IOUT = 1A, CSS = 5.6nF 35 µVRMS
(1) Subgroups are applicable for QML parts. For subgroup definitions see Section 6.6.
(2) See the 5962R23203 SMD for additional information on the QML RHA devices. 
(3) PD is the internal power dissipation. When PD exceeds 3W, the current is lowered to avoid excessive local heating (due to tester limitations).