JAJSQV1 データシート

JAJSQV1A July 2023 – October 2023 TPS7H2140-SEP

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PWP|28
- MPDS373B

サーマルパッド・メカニカル・データ

PWP|28
- PPTD351

発注情報

jajsqv1a_oa

8.3.4 Inductive-Load Switching-Off Clamp

When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp between drain and source is internally implemented, namely V_{DS_CLAMP}.

Equation 7.

V_{D S_C L A M P} = V_{I N} - V_{O U T x}

During the period of demagnetization (t_decay), the power FET is turned on for inductance-energy dissipation. The total energy is dissipated in the high-side switch (E_HSS). Total energy includes the energy of the power supply (E_IN) and the energy of the load (E_LOAD). If resistance is in series with inductance, some of the load energy is dissipated on the resistance (E_R) and the inductor itself (E_L).

Equation 8.

E_{H S S} = E_{I N} + E_{L O A D} = E_{I N} + E_{L} + E_{R}

When an inductive load switches off, E_HSS causes high thermal stressing on the device. The upper limit of the power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.

Figure 8-5 Drain-to-Source Clamping Structure

Figure 8-6 Inductive Load Switching-Off Diagram

From the perspective of the high-side switch, E_HSS equals the integration value during the demagnetization period.

Equation 9.

E_{H S S x} = \int_{0}^{t_{D E C A Y x}} V_{D S_C L A M P} \times I_{O U T x} (t) d t

Equation 10.

t_{D E C A Y x} = \frac{L}{R} \times l n (\frac{R \times I_{O U T (M A X)} + |V_{O U T}|}{|V_{O U T}|})

Equation 11.

E_{H S S x} = L \times \frac{V_{I N} + |V_{O U T}|}{R^{2}} \times \{(R \times I_{O U T (M A X)}) - [|V_{O U T}| \times l n (\frac{R \times I_{O U T (M A X)} + |V_{O U T}|}{|V_{O U T}|})]\}

When R approximately equals 0, E_HSS) can be given simply as:

Equation 12.

E_{H S S x} = \frac{1}{2} \times L \times {I^{2}}_{O U T (M A X)} \times [\frac{(V_{I N} + |V_{O U T}|)}{|V_{O U T}|}]

Figure 8-7 is a waveform of the device driving an inductive load and dissipating 40 mJ of energy across the NMOS pass-element (across IN and OUT1) during the inductive kick-back. The energy was controlled by turning off the channel # 1 at 2.8 (at I_OUT1).

The displayed signal definitions are shown in Scope Signals Description

Table 8-1 Scope Signals Description

Channel #	Name of the Signal	Signal Color
1	V_EN1	Blue
2	V_IN	Red
3	V_OUT1	Green
4	I_OUT1	Magenta
Math	E_HSS1	Cyan

The device also optimizes the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the effects of transient power and EMI to a minimum.

Figure 8-7 Inductive Load Switching-Off Waveform of 40mJ

A. The nominal inductor value use for this waveform is 8mH.

Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown in Figure 8-8 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See Figure 8-8 for more details.

Figure 8-8 Protection With External Circuitry