JAJSNL4A August   2022  – October 2022 TPS7H2221-SEP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Derating Curves
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Test Circuit and Timing Waveforms Diagrams
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 On and Off Control
      2. 8.3.2 Output Short Circuit Protection (ISC)
      3. 8.3.3 Fall Time (tFALL) and Quick Output Discharge (QOD)
        1. 8.3.3.1 QOD When System Power is Removed
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Limiting Inrush Current
        2. 9.2.2.2 Setting Fall Time for Shutdown Power Sequencing
        3. 9.2.2.3 Application Curves
    3. 9.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
    6. 10.6 Export Control Notice
    7. 10.7 Third-Party Products Disclaimer
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for IN, OUT, and GND helps minimize the parasitic electrical effects.