JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.2.1.2.2 UP and DOWN Thresholds

In this application the UP and DOWN pins are used to monitored the input voltage supply of 12V. A sequence up is started when the rail voltage is greater than 10.7 (typ) and down when the voltage is lower than 6V (typ). As the TPS7H3014 has an internal time constant (tStart_up_delay) of 2.8ms (max), a delay capacitor of 3.3μF is added to UP pin. This capacitor is added to introduce a delay in the UP pin when VIN is rising. This capacitor adds a second condition to start the sequence up, if VIN ≥ 10.7V (typ) for at least 2.8ms then the sequence up is commanded.

Fixing the upper resistor for the resistive divider in UP and DOWN, we can calculate the bottom resistor per our design requirements. The upper resistor is fixed to 10kΩ for both cases. Using the equations in Equation 19 and Equation 20, the bottom resistors for up and down are calculated as:

Equation 26. R B O T T O M _ U P = 10   k Ω ×   0.598   V 10.7   V -   0.589   V   ≅   594   Ω
Equation 27. R B O T T O M _ D O W N _______ = 10   k Ω ×   0.498   V 6   V -   0.498   V   ≅   905   Ω

Now that the reference resistors are calculated, we can select the actual (or real) resistors. In this case 0.1% tolerance resistors are used to select the closest value as:

  • RBOTTOM_UP = 619Ω
  • RBOTTOM_DOWN = 909Ω

With the actual resistor values, we can back-calculate the nominal voltage to start the sequence up and down using Equation 21 and Equation 22 as:

Equation 28. V U P _ N O M I N A L   ( V ) = 1   +   10   k Ω 619   Ω   ×   12   V   ≅   10.66   V  
Equation 29.   V D O W N _______ _ N O M I N A L ( V ) = 1   +   10   k Ω 909   Ω   ×   12   V ≅   5.97   V

The delay capacitor is calculated using Equation 23, Equation 24, and Equation 25 as:

Equation 30. R T H   ( Ω ) = 10   k Ω × 619   Ω 10   k Ω + 619   Ω   =   582.9   Ω
Equation 31. V T H   ( Ω ) = 619   Ω 10   k Ω + 619   Ω ×   12   V   =   0.7   V
Equation 32. C D E L A Y   ( F ) ≥ 0.0028   s 582.9   Ω   × l n - 0.7   V 0.598   V - 0.7   V   =   2.49   µ F

The delay capacitor is selected as 3.3μF.