JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The TPS7H3014 is a four-Channel, 3V to 14V, sequencer and supervisor for space applications. The device is intended to drive devices with enable high logic inputs. The channel count can be incremented as needed for the application by connecting multiple ICs. in a daisy-chain configuration. Each output incorporates a push-pull architecture. The logic high of these outputs are externally provided by the user by supplying a voltage to the PULL-UPx inputs. All ENx push-pull outputs are tied to the PULL_UP1 domain while SEQ_DONE and PWRGD are tied to the PULL_UP2 domain.

The SENSEx inputs are connected to the non-inverting input (undervoltage) of a comparator which is used to determine the on (in regulation) and off (not in regulation) voltage level of the monitored power supply (VOUTx). Each of these inputs feature a threshold level of 599mV (typ) with an accuracy of ±1% across: voltage, temperature, and radiation (TID). The hysteresis voltage threshold level can be adjusted by the user and determined by the RTOPx resistance and the hysteresis current (IHYS). The IHYS becomes active once the rising voltage at SENSEx exceeds the threshold (599mV typ), indicating the monitored voltage rail is in regulation. IHYS is 24μA with an accuracy of ±3% across: voltage, temperature, and radiation (TID).

The device incorporates two timers:

  1. DLY_TMR: Set the rising and falling ENx delay. Once the SENSEx-1 is above the on voltage during a sequence up, the ENx will be asserted high once the delay set by the user using the DLY_TMR input is expired. The same is true during sequence down, this means that once SENSEx is below the off voltage the ENx-1 will be asserted low once the timer is expired. This timer can be set from 0.25ms to 25ms, by using a 10.5kΩ to a 1.18MΩ, respectively.
  2. REG_TMR: Set the allowed time that a sensed voltage rail has to be above the on threshold (in regulation). Once the ENx is asserted high, the SENSEx has up to the time set by the user, using REG_TMR, to be above 599mV (typ). Otherwise a reverse sequence down from ENx-1 is started.

Separate UP and DOWN pins are provided by the device in order to enable daisy-chain configurations. The UP pin has a threshold (VTH _UP) of 599mV (typ), while the DOWN pin has an threshold (VTH _DOWN) of 498mV. A fixed hysteresis of 100mV is incorporated in both input comparators for noise stability. These pins are edge sensitive, a rising edge in UP starts the sequence up, while a falling edge in DOWN will start the sequence down.

When using a single device and driven externally, both pins (UP and DOWN) are typically tied together. Since UP and DOWN inputs have an accurate threshold, they can be used to initiate the sequence up and down by accurately sensing another rail (using a resistive divider), or they can be externally driven by a controller. Once UP is driven above VTH _UP, the device will start a sequence up by asserting EN1 high after the programmed delay time (DLY_TMR), at which point the SENSE1 will start rising up. If SENSE1 crosses the on voltage before the REG_TMR is expired, then EN2 will be asserted high after the programmed delay. This process continues until the SEQ_DONE and PWRGD are asserted high indicating a complete sequence up and system power good, respectively.

Once the DOWN pin is driven below VTH_DOWN, the device will start a sequence down by forcing EN4 low after the programmed delay. At this point, the SENSE4 voltage will start falling until is lower than the set off voltage. Once this happens, EN3 will be asserted low after the programmed delay. This will continue until EN1 is forced low. As the discharge time of the sequenced devices is unknown, the REG_TMR is not active during power down.

During sequence up, SEQ_DONE and PWRGD are asserted high after the last used channel crosses the on voltage threshold and the programmed DLY_TMR is expired (assuming it is active). During sequence down, SEQ_DONE is forced low once VOUT1 is below the off voltage and the DLY_TMR is expired. However PWRGD is forced low immediately after the commanded sequence down.

The TPS7H3014 also incorporates a comprehensive FAULT management system described in the State Machine section.