The TPS7H4001-SP can be configured in
primary-secondary mode to provide up to 72-A output current. For more details, please refer
to the EVM user's guide, TPS7H4001QEVM-CVAL Evaluation Module (EVM) User's Guide
(SLVUBW7). Figure 9-2 shows a parallel configuration that can be used to provide 36-A output.
The design procedure to configure the
primary-secondary operation using the internal oscillator is
as follows:
- The RT pin of the primary device must be left floating. This achieves two
purposes, to set the frequency to 500 kHz
(typical) using the internal oscillator and to
configure the SYNC1 and SYNC2 pins of the primary
device as output pins with a 500-kHz clock,
in-phase and 90° out of phase, respectively to the
internal oscillator of the primary device. For
more details, see Adjustable Switching Frequency and
Synchronization (SYNC) section.
- The RT pin on secondary device should be connected to a resistor such that the
frequency of the secondary device matches the
primary's frequency, 500 kHz in this case. See
Figure 8-4 for reference.
- SYNC1 and/or SYNC2 pin of the primary device must be connected to the SYNC1 pin
of the secondary device(s).
- Only a single feedback network is connected to the VSENSE pin of the primary
device. Therefore, all VSENSE pins must be
connected.
- Only a single compensation network is needed connected to the COMP pin of the
primary device. Therefore all COMP pins must be
connected.
- Only a single soft-start capacitor is needed connected to the SS pin of the
primary device. Therefore all SS pins must be
connected.
- Only a single enable signal (or resistor divider) is needed connected to the EN
pin of the primary device. Therefore all EN pins
must be connected.
- Since the primary device controls the compensation, soft-start and enable
networks, the factor of n must be taken into
account when calculating the components associated
with these pins, where n is the number of devices
in parallel.
The primary-secondary mode can also be implemented
using an external clock. In such case, a different frequency
other than 500 kHz can be used. When using an external
clock, the RT and SYNC pin configurations vary as
follows:
- RT pins of both primary and secondary device must be connected to a resistor
matching the frequency of the external clock being
used. See Figure 8-4 for reference.
- The external clock is connected to the SYNC1 pin of the primary device. A 10-kΩ
resistor to GND should be connected to the SYNC1 pin as well.
- For two devices in parallel, an inverted clock (180° out of phase respect to
the primary device) must be connected to the SYNC1
pin of the secondary device. A 10-kΩ resistor to
GND should be connected to the SYNC1 pin as well.
The SYNC2 pins of the primary and secondary
devices should be connected to VIN.
- Another option for two devices in parallel is to use a single clock connected
to the SYNC1 pins of both devices, with the SYNC2
pin of the primary device connected to VIN and the
SYNC2 pin of the secondary device connected to
GND.
- For four devices in parallel, the SYNC1 pin of each device can be supplied with a separate clock, each phase shifted 90° with respect to the other. In this configuration, all SYNC2 pins should be connected to VIN. There is also an option where two clocks can be used, where the second clock is phase shifted 90° with respect to the first. In this instance, the table below details how the SYNC1 and SYNC2 pins of each device should be configured.
Table 9-2 Pin Connections for Four Parallel Devices Using External Sync and Two ClocksDevice | SYNC1 Pin | SYNC2 Pin |
---|
1 | Clock 1 | VIN |
2 | Clock 2 | VIN |
3 | Clock 1 | GND |
4 | Clock 2 | GND |
The operation of multiple devices in parallel has
an impact on some of the component calculations. For instance, since the enable pins are all
connected together, the UVLO calculation as presented in the Enable and Adjust UVLO section will be modified according to the following
equations, in which n is the number of paralleled devices:
Equation 34. Equation 35. Also, since all SS/TR pins will be connected for
the paralleled devices, the soft-start calculation presented in the Soft-Start (SS/TR) section will be modified according to the following
equation:
Equation 36. The compensation design is detailed in the
Small Signal Model for Frequency Compensation section. The equation for
R3 changes when the COMP pins of the devices in parallel are connected:
Equation 37. Note that for parallel operation, the equations
for the other compensation components, C1 and C2, will
remain unchanged and still be calculated as shown in Equation 21 and Equation 22 due to the updated R3 calculation.