JAJSIY2D april   2019  – may 2023 TPS7H4001-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - All Devices
    6. 7.6  Electrical Characteristics: CDFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP (SHP) Option
    8. 7.8  Electrical Characteristics: HTSSOP (QMLP) Option
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Enable and Adjust UVLO
      7. 8.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 8.3.7.1 Internal Oscillator Mode
        2. 8.3.7.2 External Synchronization Mode
        3. 8.3.7.3 Primary-Secondary Operation Mode
      8. 8.3.8  Soft-Start (SS/TR)
      9. 8.3.9  Power Good (PWRGD)
      10. 8.3.10 Sequencing
      11. 8.3.11 Output Overvoltage Protection (OVP)
      12. 8.3.12 Overcurrent Protection
        1. 8.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Turn-On Behavior
      15. 8.3.15 Slope Compensation
        1. 8.3.15.1 Slope Compensation Requirements
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
          1. 9.2.2.7.1 Minimum Output Voltage
        8. 9.2.2.8 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DDW|44
  • KGD|0
  • HKY|34
サーマルパッド・メカニカル・データ
発注情報

8.3.16 Small Signal Model for Frequency Compensation

The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits shown in Figure 8-10. In Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.

The following design guidelines are provided for advanced users who prefer to compensate using the general method.

GUID-5915148D-4729-44AD-AB57-CC6645A81125-low.gif Figure 8-10 Types of Frequency Compensation

The general design guidelines for device loop compensation are as follows:

  1. Determine the crossover frequency fco. A good starting point is one-tenth of the switching frequency, ƒSW.
  2. R3 can be determined by:
    Equation 19. GUID-E2BDBFE0-1207-4CA8-9ED3-00F746540E21-low.gif

    where gmea is the transconductance of the error amplifier (1800 μS), gmps is the transconductance of the power stage (40 S) and VREF is the reference voltage (0.604 V).

  3. Place a compensation zero at the dominant pole calculated in Equation 20 using C1 and R3.
    C1 can be determined by Equation 21.
    Equation 20. GUID-3D1FBAED-E8A0-4DB5-968B-504B606D4DE8-low.gif
    Equation 21. GUID-E7632BD8-3E60-4079-BFFD-84ED5FA56BA7-low.gif
  4. C2 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output capacitor COUT.
    Equation 22. GUID-9D9BF0D3-3200-4059-9C23-FFE3DC9C9881-low.gif