The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold voltage, the device enables operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low I_q state. The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open-drain or open-collector output logic to interface with the pin.

The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150-mV typical.

If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN in split-rail applications, then the EN pin can be configured as shown in Figure 8-1, Figure 8-2, and Figure 8-3. A ceramic capacitor in parallel with the bottom resistor R₂ is recommended to reduce noise on the EN pin as used in the TPS7H4001-SP Evaluation Module. See the TPS7H4001EVM-CVAL Evaluation Module (EVM) User's Guide (SLVUBO5) for more information.

The EN pin has a small pullup current, I_p, which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function because it increases by I_h after the EN pin crosses the enable threshold. Calculate the UVLO thresholds with Equation 2 and Equation 3.

Figure 8-1 Adjustable VIN UVLO

Figure 8-2 Adjustable PVIN UVLO

Figure 8-3 Adjustable VIN and PVIN UVLO

Equation 2.

Equation 3.

where

• I_h = 3 μA
• I_p = 6.1 μA
• V_ENRISING = 1.14 V
• V_ENFALLING = 1.11 V