JAJSIY2D april 2019 – may 2023 TPS7H4001-SP
PRODMIX
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PARAMETER | TEST CONDITIONS | SUBGROUP(1) | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN AND PVIN PINS) | |||||||
PVIN operating input voltage | 1, 2, 3 | 3.0 | 7.0 | V | |||
PVIN internal UVLO threshold | PVIN rising | 1, 2, 3 | 2.425 | 2.50 | 2.575 | V | |
PVIN internal UVLO hysteresis | Load = 0 A | 1, 2, 3 | 425 | 450 | 475 | mV | |
VIN operating input voltage | 1, 2, 3 | 3.0 | 7.0 | V | |||
VIN internal UVLO threshold | VIN rising | 1, 2, 3 | 2.71 | 2.75 | 2.80 | V | |
VIN internal UVLO hysteresis | 1, 2, 3 | 134 | 150 | 178 | mV | ||
VIN shutdown supply current | VEN = 0 V | 1, 2, 3 | 2.32 | 2.85 | mA | ||
VIN operating – non switching supply current | VSENSE = VBG | 1, 2, 3 | 4 | 6 | mA | ||
ENABLE AND UVLO (EN PIN) | |||||||
Enable threshold | Rising | 1, 2, 3 | 1.110 | 1.14 | 1.172 | V | |
Falling | 1, 2, 3 | 1.080 | 1.11 | 1.148 | |||
Input current | VEN = 1.1 V | 1, 2, 3 | 4.8 | 6.1 | 7.6 | µA | |
Hysteresis current | VEN = 1.3 V | 1, 2, 3 | 2.4 | 3.0 | 3.9 | µA | |
ERROR AMPLIFIER | |||||||
Error amplifier input offset voltage | VSENSE = 0.6 V | 1, 2, 3 | –2 | 2.55 | mV | ||
VSENSE pin input current | VSENSE = 0.6 V | 1, 2, 3 | –15 | 15 | nA | ||
Error amplifier transconductance (gm) | –2 μA < ICOMP < 2 μA, V(COMP) = 1 V | 9, 10, 11 | 1150 | 1800 | 2400 | µS | |
Error amplifier DC gain(2) | VSENSE = 0.6 V | 10000 | V/V | ||||
Error amplifier source | V(COMP) = 1 V, 100-mV input overdrive | 1, 2, 3 | 100 | 140 | 190 | µA | |
Error amplifier sink | V(COMP) = 1 V, 100-mV input overdrive | 1, 2, 3 | 100 | 140 | 190 | µA | |
Error amplifier output resistance | 7 | MΩ | |||||
COMP to Iswitch gm(3) | COMP = 0.5 V | –55℃ | 3 | 28 | 38 | 49 | S |
25℃ | 1 | 29 | 40 | 50 | |||
125℃ | 2 | 30 | 41 | 52 | |||
SLOPE COMPENSATION | |||||||
Slope compensation(4) | fSW = 100 kHz, RSC = 1.1 MΩ | –1.2 | A/µs | ||||
fSW = 500 kHz, RSC = 196 kΩ | –6.0 | ||||||
fSW = 1000 kHz, RSC = 80.6 kΩ | –16.0 | ||||||
THERMAL SHUTDOWN | |||||||
Thermal shutdown | 190 | °C | |||||
Thermal shutdown hysteresis | 18 | °C | |||||
INTERNAL SWITCHING FREQUENCY | |||||||
Internally set frequency | RT = Open | VIN = 3 V | 4, 5, 6 | 444 | 473 | 515 | kHz |
VIN = 5 V | 4, 5, 6 | 449 | 502 | 560 | |||
Externally set frequency | RT = 1.07 MΩ (1%) | VIN = 3 V | 4, 5, 6 | 80 | 98 | 125 | kHz |
VIN = 5 V | 4, 5, 6 | 80 | 100 | 125 | |||
RT = 165 kΩ (1%) | VIN = 3 V | 4, 5, 6 | 455 | 495 | 535 | ||
VIN = 5 V | 4, 5, 6 | 475 | 523 | 615 | |||
RT = 73.2 kΩ (1%) | VIN = 3 V | 4, 5, 6 | 689 | 850 | 1011 | ||
VIN = 5 V | 4, 5, 6 | 760 | 986 | 1212 | |||
VIN = 5 V, TID = 100 krad(Si) | 4 | 760 | 1145 | 1425 | |||
EXTERNAL SYNCHRONIZATION | |||||||
SYNC1/SYNC2 out low-to-high rise time (10%/90%) | Cload = 25 pF | 9, 10, 11 | 70 | 180 | ns | ||
SYNC1/SYNC2 out high-to-low fall time (90%/10%) | Cload = 25 pF | 9, 10, 11 | 10 | 21 | ns | ||
SYNC2 to SYNC1 rising edge phase shift | 9, 10, 11 | 77 | 85 | 94 | ° | ||
SYNC1 falling edge delay(3) | 9, 10, 11 | 165 | 180 | 185 | ° | ||
SYNC1/SYNC2 out high level threshold | IOH = 50 µA | 1, 2, 3 | VIN – 0.3 | V | |||
SYNC1/SYNC2 out low level threshold | IOL = 50 µA | 1, 2, 3 | 600 | mV | |||
SYNC1/SYNC2 in low level threshold | PVIN = VIN = 3 V | 1, 2, 3 | 800 | mV | |||
PVIN = VIN = 5 V | 800 | ||||||
PVIN = VIN = 7 V(3) | 800 | ||||||
SYNC1/SYNC2 in high level threshold | PVIN = VIN = 3 V | 1, 2, 3 | 2.25 | V | |||
PVIN = VIN = 5 V | 3.5 | ||||||
PVIN = VIN = 7 V(3) | 4.9 | ||||||
SYNC1 in frequency range | PVIN = VIN = 5 V | 4, 5, 6 | 100 | 1000 | kHz | ||
SYNC1 in duty cycle range | Duty cycle of external clock | 4, 5, 6 | 40 | 60 | % | ||
PH (PH PIN) | |||||||
Minimum on time | Measured at 10% to 90% of VIN, IPH = 2 A, VIN = 3 V |
9, 10, 11 | 190 | 235 | ns | ||
Measured at 10% to 90% of VIN, IPH = 2 A, VIN = 5 V |
9, 10, 11 | 190 | 225 | ||||
SOFT START AND TRACKING (SS/TR PIN) | |||||||
SS charge current | 1, 2, 3 | 1.5 | 2.5 | 3 | µA | ||
SS/TR to VSENSE matching(3) | V(SS/TR) = 0.3 V | 1, 2, 3 | 30 | 90 | mV | ||
POWER GOOD (PWRGD PIN) | |||||||
VSENSE threshold | VSENSE falling (fault) | 1, 2, 3 | 90 | 91 | %VREF | ||
VSENSE rising (good) | 94 | 97 | |||||
VSENSE rising (fault) | 109 | 111 | |||||
VSENSE falling (good) | 103 | 106 | |||||
Output high leakage | VSENSE = VREF, V(PWRGD) = 5 V | 1, 2, 3 | 30 | 181 | nA | ||
Output low | I(PWRGD) = 2 mA | 1, 2, 3 | 0.3 | V | |||
Minimum VIN for valid output | V(PWRGD) < 0.5 V at 100 μA | 1, 2, 3 | 0.6 | 1 | V | ||
Minimum SS/TR voltage for PWRGD | 1, 2, 3 | 1.1 | V |