JAJSU64A April   2024  – August 2024 TPS7H4011-SP

PRODMIX  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Options Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Remote Sensing and Setting VOUT
        1. 8.3.3.1 Minimum Output Voltage
        2. 8.3.3.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Fault Input (FAULT)
      6. 8.3.6  Power Good (PWRGD)
      7. 8.3.7  Adjustable Switching Frequency and Synchronization
        1. 8.3.7.1 Internal Clock Mode
        2. 8.3.7.2 External Clock Mode
        3. 8.3.7.3 Primary-Secondary Synchronization
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Soft-Start (SS_TR)
        2. 8.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 8.3.8.3 Tracking and Sequencing
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 8.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 8.3.9.1.3 COMP Shutdown
          4. 8.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 Schottky Diode
      3. 9.2.3 Application Curve
      4. 9.2.4 Parallel Operation Compensation
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • HLB|30
サーマルパッド・メカニカル・データ
発注情報

Remote Sensing and Setting VOUT

The TPS7H4011 features a VSNS+ and VSNS- pin to enable differential remote sensing. Therefore, the effective voltage seen by the error amplifier is (VSNS+) − (VSNS-) (which is defined as VSENSE for simplicity). As shown in Figure 8-1, this can be particularly useful when powering an FPGA due to the high currents and potentially large parasitic resistances (indicated in blue). Rparasitic1 represents the parasitic resistance in the high current input voltage path powering the FPGA. This is compensated for by using a sense line from the point of load to the top of the feedback resistor divider. Rparasitic2 represents the parasitic resistance in the high current ground path. This is accounted for by connecting a sense line from the local ground to the VSNS- pin. Some FPGAs have sense lines that may utilized for this purpose. If there is no sense line, the VSNS- pin may be connected near the FPGA ground pin itself.

TPS7H4011-SP FPGA Remote Sense Example Figure 8-1 FPGA Remote Sense Example

Figure 8-2 shows the more generalized case for remote sensing.

TPS7H4011-SP  Remote Sense Diagram Figure 8-2 Remote Sense Diagram

During steady state operation, VSENSE will be equal to the reference voltage, VREF (0.6V typical). By appropriately setting the resistor divider for VSNS+ and by connecting VSNS- to the remote ground, the output voltage value across the load, VLOAD, can be set using Equation 1. TI recommends 1% tolerance or better resistors. Start with a 10kΩ for RFB_TOP and use Equation 1 to calculate RFB_BOT. To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors.

Equation 1. R F B _ B O T = V R E F V O U T ( s e t ) - V R E F × R F B _ T O P

where

  • VREF = 0.6V (typ)
  • VOUT(set) = voltage set point; this is the voltage regulated across the load

When utilizing the differential sensing feature, VSNS- is connected to the remote ground, and any voltage at the remote ground will offset the reference voltage on the non-inverting input to the error amplifier the corresponding amount (VEA+ = VREF + PGNDREMOTE). This offset at the error amplifier will then command a different output, VOUTLOCAL. This output voltage will ensure the programmed voltage is seen across the load itself, VLOAD. Therefore, it should be noted that VOUT_LOCAL will likely be a higher voltage in order to regulate VLOAD to the desired value.

If differential sensing is not required, connect VSNS- to GND. Then VREF will appear on the non-inverting input of the error amplifier. In this configuration, the behavior is the same as standard, non-differential feedback. Therefore, only Rparasitic1 is accounted for, not Rparasitic2.

VSNS+ is a high impedance input with minimal leakage current. For proper operation, VSNS- outputs a small bias current of approximately 10μA. Therefore, this current will result in a small voltage drop across Rparasitic_VSNS- and Rparasitic2. This voltage drop adds a small error term to the VSNS- pin; however, if these parasitic resistances are minimized, the error term is generally negligible.

This remote sensing architecture is capable of sensing offsets between the remote and local ground of ±100mV. Therefore, the difference between PGNDLOCAL and PGNDREMOTE must be under 100mV.