JAJSU64A April   2024  – August 2024 TPS7H4011-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Remote Sensing and Setting VOUT
        1. 8.3.3.1 Minimum Output Voltage
        2. 8.3.3.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Fault Input (FAULT)
      6. 8.3.6  Power Good (PWRGD)
      7. 8.3.7  Adjustable Switching Frequency and Synchronization
        1. 8.3.7.1 Internal Clock Mode
        2. 8.3.7.2 External Clock Mode
        3. 8.3.7.3 Primary-Secondary Synchronization
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Soft-Start (SS_TR)
        2. 8.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 8.3.8.3 Tracking and Sequencing
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 8.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 8.3.9.1.3 COMP Shutdown
          4. 8.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 Schottky Diode
      3. 9.2.3 Application Curve
      4. 9.2.4 Parallel Operation Compensation
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HLB|30
サーマルパッド・メカニカル・データ
発注情報

8.3.6 Power Good (PWRGD)

The PWRGD pin is an open-drain output that is asserted when the output voltage reaches an appropriate range. The PWRGD pin may be pulled-up through a resistor to VOUT or to another voltage level within the device recommended operating conditions. Select the resistor size to keep the maximum current sunk by PWRGD to under the recommended operating condition current maximum of 2mA. Generally a pull up resistor of 10kΩ is sufficient. Using a larger value resistor will minimize power dissipation but may allow switching noise to couple into the PWRGD signal due to the weaker pull-up.

PWRGD will be asserted or deasserted when VOUT is within a certain percentage of its programmed value. This is accomplished by comparing the voltage on VSENSE (VSENSE = VSNS+ − VSNS-) to (VREF + VSNS-). This enables the use of the same power good levels whether or not differential remote sensing is utilized. If differential remote sensing is not utilized (which means VSNS- = GND), then it is simplified so that the voltage on VSNS+ is compared to VREF.

For example, when VSENSE reaches PWRGDLOW_R% (typically 95%) of its final value, PWRGD is asserted. When VSENSE falls below PWRGDLOW_F% (typically 92%), PWRGD is deasserted. See Figure 8-5 for these waveforms.

TPS7H4011-SP Power Good Low Thresholds Figure 8-5 Power Good Low Thresholds

Power good also has a threshold if an overvoltage event occurs on VOUT. For example, when VSENSE reaches PWRGDHIGH_R% (typically 108%) of its final value, PWRGD is deasserted. When VSENSE falls below PWRGDHIGH_F% (typically 105%), PWRGD is asserted. See Figure 8-6 for these waveforms.

TPS7H4011-SP Power Good High Thresholds Figure 8-6 Power Good High Thresholds

The PWRGD is in a defined state when the VIN input voltage is greater than 2V but has reduced current sinking capability. The PWRGD achieves full current sinking capability by the time VIN reaches 4.5V. See VINMIN_PWRGD in the Electrical Characteristics.

In addition to the description of PWRGD above, PWRGD is deasserted during other conditions that cause regulation to stop such as:

  • VIN or PVIN are in UVLO
  • The device is in thermal shutdown
  • The device EN pin is deasserted
  • The device FAULT pin is asserted
  • the COMP pin reaches the COMPSHDN threshold (1.9V typical)