The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. The OVP circuit engages when VSENSE ≥ [PWRGD_{HIGH_R%} × (V_REF + VSNS-)]. Typically, this means the OVP circuitry engages when VOUT rises above 108% of its nominal value. When OVP is active, the high-side FET stays off and the low-side FET stays on to quickly discharge VOUT.

An example that could cause an overvoltage condition is when the power supply output is overloaded for a sustained period of time. Therefore, the error amplifier compares the actual output voltage to the reference voltage. If the VSENSE pin voltage is lower than the reference voltage for a considerable time, the output of the error amplifier demands maximum output current. After the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes this overshoot.

If the VSENSE pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off, preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.