Layout is a critical portion of good power supply
design. See Layout Example for a PCB layout
example.
It is recommended to include a large topside area
filled with ground. This top layer ground area should be connected to the internal ground
layers using vias at the input bypass capacitor, the output filter capacitor, and directly
under the TPS7H4011 device in order to provide a thermal path from the exposed thermal pad
to ground. The topside ground area together with the internal ground plane must provide
adequate heat dissipating area.
It is recommended that the thermal pad under the
TPS7H4011 is tied to GND on internal ground layers utilizing vias. The thermal pad does
not need to directly connect to ground on the top layer in order to provide noise
isolation between the thermal pad ground and the topside PGND, which may be noisy.
There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic
capacitance to generate noise or degrade the power supply's performance. To help eliminate
these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with an X7R dielectric.
Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections.
The VIN pin must also be bypassed to ground using
a low ESR ceramic capacitor with an X7R dielectric. Make sure to connect this
capacitor to the quieter analog ground trace (if utilized) rather than the power
ground trace of the PVIN bypass capacitor.
Since the SW connection is the switching node,
the output inductor should be located close to the SW pins and the PCB conductor area
minimized to prevent excessive capacitive coupling.
The output filter capacitor ground should use the
same power ground as the PVIN input bypass
capacitor. Try to minimize this conductor length
while maintaining adequate width.
It is critical to keep the feedback trace away from inductor EMI and other
noise sources. Run the feedback trace as far from
the inductor, switch (SW) node, and noisy power
traces as possible. Avoid routing this trace
directly under the output inductor if possible. If
not possible, ensure that the trace is routed on
another layer with a ground layer separating the
trace and inductor.
Keep the resistive divider used to generate the VSNS+ voltage as close to the
device pin as possible in order to reduce noise pickup.
The RT and COMP pins are sensitive to noise, so
components around these pins should be located as close as possible to the IC and routed
with minimal trace lengths.
Make all of the power (high current) traces as short, direct, and thick as possible.
It may be
possible to obtain acceptable performance with alternate PCB layouts.