SLVSAI0J October   2010  – May 2016 TPS82670 , TPS82671 , TPS826711 , TPS826716 , TPS82672 , TPS826721 , TPS82673 , TPS82674 , TPS826745 , TPS82675 , TPS82676 , TPS826765 , TPS82677

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Save Mode
      2. 9.3.2 Mode Selection
      3. 9.3.3 Spread Spectrum, PWM Frequency Dithering
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable
      2. 9.4.2 Soft Start
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input Capacitor Selection
        2. 10.2.2.2 Output Capacitor Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Surface Mount Information
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 References
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI (3) Voltage at VIN(2) –0.3 6 V
Voltage at VIN (TPS826721)(2) -0.3 5.5
Voltage at VOUT –0.3 3.6 V
Voltage at EN, MODE –0.3 VIN + 0.3 V
Power dissipation Internally limited
TA Operating temperature range(4) –40 85 °C
TINT (max) Maximum internal operating temperature 125 °C
Tstg Storage temperature –55 125 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operation above 4.8V input voltage for extended periods may affect device reliability.
(3) All voltage values are with respect to network ground terminal.
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating temperature (TINT(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA(max)= TJ(max)–(RθJA X PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum internal temperature of 105°C.

8.2 ESD Ratings

VALUE UNIT
VESD(1) Human body model (HBM) ESD stress voltage(2) ±2000 V
Charge device model (CDM) ESD stress voltage(3) ±1000
Machine model (MM) ESD stress voltage(4) ±200 V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(4) The machine model is a 200-pF capacitor discharged directly into each pin.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage range 2.3 4.8(2) V
IO Output current range TPS82671 to TPS826765 0 600 mA
Additional output capacitance (PFM/PWM operation)(1) TPS82670 to TPS82676
TPS826711, TPS826716, TPS826721, TPS826765, TPS8267195		 0 2.5 µF
TPS82677 0 4 µF
Additional output capacitance (PWM operation)(1) 0 7 µF
TA Ambient temperature –40 +85 °C
TJ Operating junction temperature –40 +125 °C
(1) In certain applications larger capacitor values can be tolerable, see Output Capacitor Selection section for more details.

8.4 Thermal Information

THERMAL METRIC(1) TPS8267x UNIT
SIP
8 PINS
RθJA Junction-to-ambient (top) thermal resistance 125 °C/W
Junction-to-ambient (bottom) thermal resistance 70
RθJCtop Junction-to-case (top) thermal resistance -
RθJB Junction-to-board thermal resistance -
ψJT Junction-to-top characterization parameter -
ψJB Junction-to-board characterization parameter -
RθJCbot Junction-to-case (bottom) thermal resistance -
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 1.8V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT = 1.8V, EN = 1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ Operating quiescent current IO = 0mA. Device not switching 17 40 μA
IO = 0mA. PWM operation 5.8 mA
ISD Shutdown current EN = GND 0.5 5 μA
UVLO Undervoltage lockout threshold TPS8267195 only 2.08 2.14 V
all other versions 2.05 2.1
PROTECTION
Thermal shutdown 140 °C
Thermal shutdown hysteresis 10 °C
ILIM Peak Input Current Limit 1100 mA
ISC Input current limit under short-circuit conditions VO shorted to ground 13.5 mA
ENABLE, MODE
VIH High-level input voltage 1.0 V
VIL Low-level input voltage 0.4 V
Ilkg Input leakage current Input connected to GND or VIN 0.01 1.5 μA
OSCILLATOR
fSW Oscillator frequency IO = 0mA. PWM operation 4.9 5.45 6.0 MHz
OUTPUT
VOUT Regulated DC output voltage TPS82670
TPS82671
TPS826711
TPS826716
TPS82672
TPS826721
TPS82673
TPS82674
TPS826745
TPS82675
TPS82676
TPS826765		 2.5V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 600 mA
PFM/PWM operation		 0.98×VNOM VNOM 1.03×VNOM V
2.5V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 600 mA
PFM/PWM operation		 0.98×VNOM VNOM 1.04×VNOM V
2.5V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 600 mA
PWM operation		 0.98×VNOM VNOM 1.02×VNOM V
TPS8267195 2.5V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 600 mA
PFM/PWM operation		 0.975×VNOM VNOM 1.035×VNOM V
2.5V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 600 mA
PFM/PWM operation		 0.975×VNOM VNOM 1.045×VNOM V
2.5V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 600 mA
PWM operation		 0.975×VNOM VNOM 1.025×VNOM V
TPS82677 2.5V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 600 mA
PFM/PWM operation		 0.98×VNOM VNOM 1.04×VNOM V
2.5V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 600 mA
PWM operation		 0.98×VNOM VNOM 1.02×VNOM V
Line regulation VI = VO + 0.5V (min 2.5V) to 5.5V, IO = 200 mA 0.23 %/V
Load regulation IO = 0mA to 600 mA. PWM operation –0.00085 %/mA
Feedback input resistance 480 kΩ
ΔVO Power-save mode ripple voltage TPS82671
TPS826711		 IO = 1mA, VO = 1.8V 19 mVPP
TPS826716 IO = 1mA, VO = 1.6V 19 mVPP
TPS826721 IO = 1mA, VO = 2.1V 19 mVPP
TPS82673
TPS82674
TPS826745
TPS82675		 IO = 1mA, VO = 1.2V 16 mVPP
TPS82676 IO = 1mA, VO = 1.1V 16 mVPP
TPS826765 IO = 1mA, VO = 1.05V 16 mVPP
TPS82677 IO = 1mA, VO = 1.2V 25 mVPP
Start-up time TPS82671
TPS826711		 IO = 0mA, Time from active EN to VO 120 μs
rDIS Discharge resistor for power-down sequence Devices featuring active discharge 70 150 Ω

8.6 Typical Characteristics

TPS82670 TPS82671 TPS82672 TPS82673 TPS82674 TPS82675 TPS82676 TPS82677 TPS826711 TPS826716 TPS826721 TPS826745 TPS826765 TPS8267195 iq1_vi_lvs952.gif
Figure 1. Quiescent Current vs. Input Voltage
TPS82670 TPS82671 TPS82672 TPS82673 TPS82674 TPS82675 TPS82676 TPS82677 TPS826711 TPS826716 TPS826721 TPS826745 TPS826765 TPS8267195 PSRR2_f_lvsai0.gif
VI = 3.6 V VO = 1.8 V (TPS82671)
Figure 3. Power Supply Rejection Ratio vs. Frequency
TPS82670 TPS82671 TPS82672 TPS82673 TPS82674 TPS82675 TPS82676 TPS82677 TPS826711 TPS826716 TPS826721 TPS826745 TPS826765 TPS8267195 onois_1v8pwm_lvsai0.gif
VO = 1.8 V RL = 12 Ω (TPS82671)
Figure 5. Spurious Output Noise (PWM Mode) vs. Frequency
TPS82670 TPS82671 TPS82672 TPS82673 TPS82674 TPS82675 TPS82676 TPS82677 TPS826711 TPS826716 TPS826721 TPS826745 TPS826765 TPS8267195 fs_vi_lvsai0.gif
VO = 1.8 V
Figure 2. PWM Switching Frequency vs. Input Voltage
TPS82670 TPS82671 TPS82672 TPS82673 TPS82674 TPS82675 TPS82676 TPS82677 TPS826711 TPS826716 TPS826721 TPS826745 TPS826765 TPS8267195 onois_1v8pfm_lvsai0.gif
VO = 1.8 V RL = 150 Ω (TPS82671)
Figure 4. Spurious Output Noise (PFM Mode) vs. Frequency
TPS82670 TPS82671 TPS82672 TPS82673 TPS82674 TPS82675 TPS82676 TPS82677 TPS826711 TPS826716 TPS826721 TPS826745 TPS826765 TPS8267195 nois_den_lvsai0.gif
VI = 3.6 V VO = 1.8 V (TPS82671)
Figure 6. Output Spectral Noise Density vs. Frequency