The TPS92512 requires a proper layout for optimal performance. The following section gives some guidelines to ensure a proper layout.

11.1 Layout Guidelines

An example of a proper layout for the TPS92512 is shown in Figure 17. Creating a large GND plane under the integrated circuit (IC) for good electrical and thermal performance is important.

• The GND pin of the device must connect to the GND plane directly beneath the IC.
• Thermal vias can be used to connect the topside GND plane to additional printed-circuit board (PCB) layers for heat spreading and more solid grounding.
• The input capacitors must be located as close as possible to the VIN pin and the GND plane and should be tied to a solid backside ground plane using multiple vias.
• The compensation components must be located as close as possible to the COMP and GND pins in order to minimize noise sensitivity.
• The PH trace must be kept as short as possible to reduce the possibility of radiated noise/EMI.
• The ISENSE node should be kept as short as possible and shielded from noise.
• The RT/CLK pin is sensitive and its routing must be kept as short as possible.
• In higher current applications, routing the load current of the current-sense resistor to the junction of the input capacitor and rectifier diode GND node may be necessary. The easiest way to accomplish this is to use a backside ground plane and arrays of vias to connect the top side ground connections solidly to the backside plane. This steers the high current away from the sensitive RT/CLK to GND connection.
• If possible, the current loop created when the internal MOSFET is on should be in the same direction as the current loop when the internal MOSFET is off and the schottky diode is conducting. This will prevent magnetic field reversal, reduce radiated noise, and simplify EMI filtering.

11.2 Layout Example

Figure 17. Layout Example