SLVSCT1B February   2015  – April 2015 TPS92512 , TPS92512HV

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout and Low Power Shutdown (UVLO Pin)
      2. 8.3.2 Adjustable Switching Frequency (RT/CLK Pin)
      3. 8.3.3 Synchronizing the Switching Frequency to an External Clock (RT/CLK Pin)
      4. 8.3.4 Adjustable LED Current (IADJ and ISENSE Pins)
      5. 8.3.5 PWM Dimming (PDIM Pin)
      6. 8.3.6 External Compensation (COMP Pin)
      7. 8.3.7 Overcurrent Protection
      8. 8.3.8 Overtemperature Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up
      2. 8.4.2 Minimum Pulse Width and Limitations
      3. 8.4.3 Maximum Duty Cycle and Bootstrap Voltage (BOOT)
      4. 8.4.4 Thermal Shutdown and Thermal Limitations
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selection
      2. 9.1.2 Input Capacitor Selection
      3. 9.1.3 Output Capacitor Selection
      4. 9.1.4 Rectifier Diode Selection
      5. 9.1.5 Output Protection Clamp (Optional)
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
      1. 9.4.1 Standard Component Selection
      2. 9.4.2 Calculate UVLO Resistor Values
      3. 9.4.3 Calculate the RT Resistor Value (RRT)
      4. 9.4.4 Calculate the ISENSE Resistor Value (R(ISENSE))
      5. 9.4.5 Calculate the Inductor Value and Operating Parameters (L)
      6. 9.4.6 Calculate the Minimum Input Capacitance and the Required RMS Current Rating (CIN)
      7. 9.4.7 Calculate the Output Capacitor Value (COUT)
      8. 9.4.8 Calculate the Diode Power Dissipation (D)
    5. 9.5 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DGQ (HVSSOP) Package
Top View
TPS92512 TPS92512HV pinout_slvsct1.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is recharged.
COMP 8 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin.
GND 9 G Ground.
IADJ 6 I Analog current adjust pin. The voltage applied to this pin will set the current sense (ISENSE pin) voltage. The range of the ADJ pin is 180 mV to 1.8 V and the corresponding ISENSE pin voltage is the IADJ pin voltage divided by 6.
ISENSE 7 I Inverting node of the transconductance (gM) error amplifier.
PDIM 4 I PWM dimming input pin. The duty cycle of the PWM signal linearly controls the average output current of the converter.
PH 10 O The source of the internal high-side MOSFET.
PowerPAD PAD G GND pin must be electrically connected to the exposed pad directly beneath the device on the printed circuit board for proper operation.
RT/CLK 5 I Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to program the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin becomes a high impedance clock input to the internal PLL. If the clocking edges stop, the internal amplifier is re-enabled and the mode returns to the resistor-programmed function.
UVLO 3 I Adjustable undervoltage lockout. Set with resistor divider from VIN.
VIN 2 P Input supply voltage, 4.5V to 42V or 4.5V to 60V for the HV version.
(1) I = Input, O = Output, P = Supply, G = Ground