JAJSIW2 April   2020 TPS92612

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     代表的なアプリケーションの図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias
        1. 7.3.1.1 Power-On Reset (POR)
      2. 7.3.2 Constant-Current Driver
      3. 7.3.3 PWM Control
      4. 7.3.4 Protection
        1. 7.3.4.1 Short-to-GND Protection
        2. 7.3.4.2 Over Temperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout, V(SUPPLY)< V(POR_rising)
      2. 7.4.2 Normal State, V(SUPPLY) ≥ 4.5 V
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Single LED Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Single-Channel LED Driver With Heat Sharing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Timing Requirements

MIN NOM MAX UNIT
t(PWM_delay_rising) PWM rising edge delay, 50% PWM voltage to 10% of output current closed loop, t2 - t1 as shown in Figure 1 10 17 25 µs
t(PWM_delay_falling) PWM falling edge delay, 50% PWM voltage to 90% of output current open loop, t5 - t4 as shown in Figure 1 15 21 30 µs
t(DEVICE_STARTUP) SUPPLY rising edge to 10% output current at 50-mA set current, t8 - t7 as shown
in Figure 1
100 150 µs
t(SG_deg) Output short-to-ground detection deglitch time 80 125 175 µs
t(TSD_deg) Thermal over temperature deglitch timer 50 µs
t(Recover_deg) Fault recovery deglitch timer 8.5 16 25 µs
TPS92612 tps92612-output-timing-diagram.gifFigure 1. Output Timing Diagram