JAJSKJ6 June   2021 TPS92633

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply (SUPPLY)
        1. 7.3.1.1 Power-On Reset
        2. 7.3.1.2 Supply Current in Fault Mode
      2. 7.3.2  Enable and Shutdown (EN)
      3. 7.3.3  Reference Current (IREF)
      4. 7.3.4  Constant-Current Output and Setting (INx)
      5. 7.3.5  Analog Current Control (ICTRL)
        1. 7.3.5.1 Off-Board Brightness Binning Resistor
        2. 7.3.5.2 NTC Resistor
      6. 7.3.6  Thermal Sharing Resistor (OUTx and RESx)
      7. 7.3.7  PWM Control (PWMx)
      8. 7.3.8  Supply Control
      9. 7.3.9  Diagnostics
        1. 7.3.9.1 IREF Short-to-GND Detection
        2. 7.3.9.2 IREF Open Detection
        3. 7.3.9.3 LED Short-to-GND Detection
        4. 7.3.9.4 LED Open-Circuit Detection
        5. 7.3.9.5 Single LED Short-Circuit Detection (SLS_REF)
        6. 7.3.9.6 LED Open-Circuit and Single LED Short-Circuit Detection Enable (DIAGEN)
        7. 7.3.9.7 Low Dropout Operation
        8. 7.3.9.8 Over-Temperature Protection
      10. 7.3.10 FAULT Bus Output With One-Fails–All-Fail
      11. 7.3.11 FAULT Table
      12. 7.3.12 LED Fault Summary
      13. 7.3.13 IO Pins Inner Connection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout, V(SUPPLY) < V(POR_rising)
      2. 7.4.2 Normal Operation V(SUPPLY) ≥ 4.5 V
      3. 7.4.3 Low-Voltage Dropout Operation
      4. 7.4.4 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 BCM Controlled Rear Lamp with One-Fails-All-Fail Setup
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Independent PWM Controlled Rear Lamp with Off Board LED and Binning Resistor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

V(SUPPLY) = 5 V to 40 V, V(EN) = 5V, TJ = –40°C to +150°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(POR_rising) Supply voltage POR rising threshold 3.6 4 V
V(POR_falling) Supply voltage POR falling threshold 3.0 3.4 V
I(SD) Device shutdown current V(EN) = 0 V 14 26 µA
I(Quiescent) Device standby ground current PWM = HIGH 1.5 2.5 mA
I(Fault) Device supply current in fault mode PWM = HIGH, FAULT externally pulled LOW 0.21 0.330 0.45 mA
LOGIC INPUTS (EN, DIAGEN, PWM)
VIL(EN) Input logic-low voltage, EN 0.7 V
VIH(EN) Input logic-high voltage, EN 2.0 V
I(EN_pulldown) EN pulldown current V(EN) = 12 V 1.5 3.3 4.5 µA
VIL(DIAGEN) Input logic-low voltage, DIAGEN 1.045 1.1 1.155 V
VIH(DIAGEN) Input logic-high voltage, DIAGEN 1.14 1.2 1.26 V
VIL(PWM) Input logic-low voltage, PWM 1.045 1.1 1.155 V
VIH(PWM) Input logic-high voltage, PWM 1.14 1.2 1.26 V
CONSTANT-CURRENT DRIVER
I(OUTx_Tot) Device output-current for each channel 100% duty cycle 5 150 mA
V(CS_REG) Sense-resistor regulation voltage TA = –40°C to +125°C, ICTRL ground 46 50 54 mV
TA = –40°C to +125°C, V(ICTRL) = 0.6745 V 95 100 105
TA = –40°C to +125°C, V(ICTRL) = 1.349 V 192 200 208
TA = –40°C to +125°C, V(ICTRL) = 2.698 V 384 400 416
ΔV(CS_c2c) Channel to channel mismatch ΔV(CS_c2c) = 1 – V(CS_REGx)/Vavg(CS_REG), V(ICTRL) = 0.68 V –3 +3 %
ΔV(CS_c2c) = 1 – V(CS_REGx)/Vavg(CS_REG), V(ICTRL) = 1.365 V –3 +3
ΔV(CS_d2d) Device to device mismatch ΔV(CS_d2d) = 1 – Vavg(CS_REG)/Vnom(CS_REG), V(ICTRL) = 0.68 V –4 +4 %
ΔV(CS_d2d) = 1 – Vavg(CS_REG)/Vnom(CS_REG), V(ICTRL) = 1.365 V –4 +4
R(CS_REG) Sense-resistor range 0.65 20 Ω
V(DROPOUT) Voltage dropout from INx to OUTx, RESx open current setting of 100 mA 200 400 mV
current setting of 150 mA 300 600
Voltage dropout from INx to RESx, OUTx open current setting of 100 mA 280 600 mV
current setting of 150 mA 400 900
I(RESx) Ratio of RESx current to total current I(RESx)/I(OUTx_Tot), V(INx) – V(RESx) > 1 V 95 %
V(IREF) IREF voltage 1.235 V
N(ICTRL) ICTRL current output ratio I(ICTRL)/I(IREF) 9.7 10 10.3
V(ICTRL_SAT) ICTRL saturated voltage V(CS_REG) = 400 mV 2.75 V
V(CS_SAT) V(SUPPLY) – V(IN) V(ICTRL) = 3 V 410 mV
DIAGNOSTICS
V(OPEN_th_rising) LED open rising threshold, V(IN) – V(OUT) 180 300 420 mV
V(OPEN_th_falling) LED open falling threshold, V(IN) – V(OUT) 450 mV
V(SG_th_rising) Channel output short-to-ground rising threshold 1.14 1.2 1.26 V
V(SG_th_falling) Channel output short-to-ground falling threshold 0.855 0.9 0.945 V
N(SLS_REF) SLS_REF current output ratio I(SLS_REF)/I(IREF) 0.97 1 1.03
N(OUT) OUT voltage attenuation ratio V(OUT) = 3 to 14 V. 3.84 4 4.16
I(Retry) Channel output V(OUT) short-to-ground retry current 0.64 1.08 1.528 mA
I(IREF_OPEN_th) IREF open threshold 8 µA
V(IREF_SHORT_th) IREF short-to-ground threshold 0.6 V
I(IREF_ST_Clamp) Current clamp for IREF shor-to-GND 418 µA
FAULT
VIL(FAULT) Logic input low threshold 0.7 V
VIH(FAULT) Logic input high threshold 2 V
t(FAULT_rising) Fault detection rising edge deglitch time 10 µs
t(FAULT_falling) Fault detection falling edge deglitch time 10 µs
I(FAULT_pulldown) FAULT internal pulldown current V(FAULT) = 0.4 V 2 3 4 mA
I(FAULT_pullup) FAULT internal pullup current 6 10 14 µA
I(FAULT_leakage) FAULT leakage current V(FAULT) = 40 V 1 2 µA
THERMAL PROTECTION
T(TSD) Thermal shutdown junction temperature threshold 157 172 187 °C
T(TSD_HYS) Thermal shutdown junction temperature hysteresis 15 °C