JAJSHS0C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
LHILIM register configures the ILIM event counter and the VILIM(THR) of channel-1 and channel-2. The settings in this register are applied when LH pin is set high.
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
---|---|---|---|---|---|---|---|---|---|---|
1Eh | LHILIM | LHCH2ILIMCNT1:0 | LHCH1ILIMCNT1:0 | LHCH2ILIM1:0 | LHCH1ILIM1:0 | 00001111 |
LHILIM-counter counts the number of ILIM fault events before disabling the associated channel completely or initiating the ILIM Fault Timer.
00: ILIM event counter threshold = 1
01: ILIM event counter threshold = 4
10: ILIM event counter threshold = 16
11: ILIM event counter threshold = 32
00: VILIM(THR) = 75 mV
01: VILIM(THR) = 100 mV
10: VILIM(THR) = 150 mV
11: VILIM(THR) = 250 mV