JAJSKY0B June   2019  – July 2024 TPS99001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Analog to Digital Converter
    6. 5.6  Electrical Characteristics—Voltage Regulators
    7. 5.7  Electrical Characteristics—Temperature and Voltage Monitors
    8. 5.8  Electrical Characteristics—Current Consumption
    9. 5.9  Power-Up Timing Requirements
    10. 5.10 Power-Down Timing Requirements
    11. 5.11 Timing Requirements—Sequencer Clock
    12. 5.12 Timing Requirements—Host and Diagnostic Port SPI Interface
    13. 5.13 Timing Requirements—ADC Interface
    14. 5.14 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog to Digital Converter
        1. 6.3.1.1 Analog to Digital Converter Input Table
      2. 6.3.2 Power Sequencing and Monitoring
        1. 6.3.2.1 Power Monitoring
      3. 6.3.3 DMD Mirror Voltage Regulator
      4. 6.3.4 Low Dropout Regulators
      5. 6.3.5 System Monitoring Features
        1. 6.3.5.1 Windowed Watchdog Circuits
        2. 6.3.5.2 Die Temperature Monitors
        3. 6.3.5.3 External Clock Ratio Monitor
      6. 6.3.6 Communication Ports
        1. 6.3.6.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 PARKING
      6. 6.4.6 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Headlight
        1. 7.2.1.1 Design Requirements
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99001-Q1 Power Supply Architecture
    2. 8.2 TPS99001-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 Kelvin Sensing Connections
      5. 9.1.5 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.9 Power-Up Timing Requirements

TYP UNIT
ten_dly PROJ_ON to 1.1V enable. This includes PROJ_ON tglitch time. Rising edge of PROJ_ON to rising edge of 1.1V enable 11 ms
tmon1(1)(2) Maximum time for 1.1V rail to reach voltage threshold after enable has been asserted. This delay length will occur even if 1.1V meets threshold earlier. Rising edge of ENB_1P1V to internal 1.1V monitor test (3) 10 ms
tmon2(1)(2) Maximum time for 1.8V rail to reach voltage threshold after enable has been asserted. This delay length will occur even if 1.8V meets threshold earlier. Rising edge of ENB_1P8V to internal 1.8V monitor test (3) 10 ms
tmon3(1)(2) Maximum time for 3.3V rail to reach voltage threshold after enable has been asserted. This delay length will occur even if 3.3V meets threshold earlier. Rising edge of ENB_3P3V to internal 3.3V monitor test (3) 10 ms
tw1(4) RESETZ delay after voltage testing completion. Completion of 3.3V monitor test to RESETZ rising edge 10 ms
(1) V1P1V, V1P8V, and V3P3V rails may be enabled prior to the TPS99001-Q1 assertion of their respective enable signal if required for system power design. If necessary, ENB_1P1V may be connected to the 1.1V, 1.8V, and 3.3V external supply enables.
(2) If any voltage threshold is not met within the specified time, the TPS99001-Q1 will not deassert RESETZ. The power-up procedure must be fully restarted in this situation.
(3) Each TPS monitor test is performed approximately 10 ms from the voltage rail’s respective voltage enable. The voltage rail may come to its threshold value any time before this. This means there should be approximately 10 ms between each enable. The time for the respective 1.1V, 1.8V, and 3.3V to come up will differ by design and parts chosen, but they must all be valid before the monitor test.
(4) tw1 starts after the 3.3V rail passes its internal monitor tests (~10 ms). This time does not start as soon as the 3.3V comes to its threshold value. This time starts after the internal TPS monitor check for 3.3V passes. After the test passes, there will be a 10 ms delay before RESETZ may be de-asserted. This means there will be approximately 20 ms delay from the time the 3.3V enable is valid to the time RESETZ is de-asserted.
TPS99001-Q1 Power Up Timing Figure 5-1 Power Up Timing