JAJSN97D November   2021  – August 2023 TPSI3050-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.3 Application Curves

GUID-20220912-SS0I-953T-LF8X-MJKPWHH3XT3P-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 9.09 kΩ
CDIV1 = 470 nF CDIV2 = 470 nF
IAUX = 0 mA CVDRV = 10 nF TA = 25°C
Figure 9-4 Power Up, VEN = VVDDP, Three-Wire Mode, TPSI3050-Q1
GUID-20220912-SS0I-DQVS-T7MZ-7HRWFQQBP79D-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 9.09 kΩ
CDIV1 = 470 nF CDIV2 = 470 nF
IAUX = 0 mA CVDRV = 10 nF TA = 25°C
Figure 9-6 tHL_VDRV, Three-Wire Mode, TPSI3050-Q1
GUID-20220912-SS0I-JM4P-PGXR-TRGMCJDJK0FW-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 12.7 kΩ
CDIV1 = 330 nF CDIV2 = 680 nF
IAUX = 4 mA CVDRV = 10 nF TA = 25°C
Figure 9-8 Power Up, VEN = VVDDP, Three-Wire Mode,
TPSI3050-Q1
GUID-20220912-SS0I-VBG8-7VMS-QT4WZBPGFBKC-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 12.7 kΩ
CDIV1 = 330 nF CDIV2 = 680 nF
IAUX = 4 mA CVDRV = 10 nF TA = 25°C
Figure 9-10 tHL_VDRV, Three-Wire Mode, TPSI3050-Q1
GUID-20220912-SS0I-X1MK-BZD4-V78JXX9KGNNB-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 9.09 kΩ
CDIV1 = 470 nF CDIV2 = 470 nF
IAUX = 0 mA CVDRV = 10 nF TA = 25°C
Figure 9-5 tLH_VDRV, Three-Wire Mode, TPSI3050-Q1
GUID-20220912-SS0I-RHWM-ZQ86-RFZPXGJH6LQB-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 9.09 kΩ
CDIV1 = 470 nF CDIV2 = 470 nF
IAUX = 0 mA CVDRV = 10 nF TA = 25°C
Figure 9-7 Three-Wire Mode, fEN = 10 kHz, TPSI3050-Q1
GUID-20220912-SS0I-ZDB3-WQ0L-0DFJCVGVBPZH-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 12.7 kΩ
CDIV1 = 330 nF CDIV2 = 680 nF
IAUX = 4 mA CVDRV = 10 nF TA = 25°C
Figure 9-9 tLH_VDRV, Three-Wire Mode, TPSI3050-Q1
GUID-20220912-SS0I-MHS5-BHX8-GR7WGV5GNFSN-low.png
Three-wire mode VDDP = 5.0 V RPXFR = 12.7 kΩ
CDIV1 = 330 nF CDIV2 = 680 nF
IAUX = 4 mA CVDRV = 10 nF TA = 25°C
Figure 9-11 Three-Wire Mode, fEN = 10 kHz, TPSI3050-Q1