JAJSNL0C April   2022  – August 2023 TPSI3050

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4 Device Functional Modes

Table 8-3 summarizes the functional modes for the TPSI3050 and TPSI3050S.

Table 8-3 TPSI3050, TPSI3050S Device Functional Modes
VDDP(6)VDDHEN(6)VDRVCOMMENTS
Powered up(2)Powered up(4)LLTPSI3050 normal operation:
VDRV output state assumes logic state of EN logic state.
HH
L L TPSI3050S normal operation (three-wire mode only):
rising edge of EN causes VDRV to be singly pulsed high. EN must be asserted low first to assert another pulse.
L → HL → H → L
Powered down(3)Powered down(5)X(1)LDisabled operation:
VDRV output disabled, keep off circuitry applied.
Powered up(2)Powered down(5)X(1)LDisabled operation:
VDRV output disabled, keep off circuitry applied.
Powered down(3)Powered up(4)X(1)LDisabled operation:
when VDDP is powered down, output driver is disabled automatically after timeout, keep off circuitry applied.
(1) X: do not care.
(2) VVDDP ≥ VDDP undervoltage lockout rising threshold, VVDDP_UV_R.
(3) VVDDP < VDDP undervoltage lockout falling threshold, VVDDP_UV_F.
(4) VVDDH ≥ VDDH undervoltage lockout rising threshold, VVDDH_UV_R.
(5) VVDDH < VDDH undervoltage lockout falling threshold, VVDDH_UV_F.
(6) Refer to Power Supply and EN Sequencing for additional information.