JAJSNT3B April   2022  – August 2023 TPSI3052

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
CREEPAGE AND TRACKING
CLR External clearance(1) Shortest terminal-to-terminal distance through air ≥ 8.5 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface ≥ 8.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) ≥ 120 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material Group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1414 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave) 1000 VRMS
DC voltage 1414 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM; t = 60 s (qualification test) 4243 VPK
VTEST = 1.2 × VIOTM; t = 1 s (100% production test) 5091 VPK
VIMP Maximum impulse voltage(3) Tested in air;
1.2/50-µs waveform per IEC 62638-1		 4500 VPK
VIOSM Maximum surge isolation voltage(3) Tested in oil (qualification test);
1.2/50-µs waveform per IEC 62638-1		 5850 VPK
qpd Apparent charge(4) Method a: After input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s.		 ≤ 5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.3 × VIORM, tm = 10 s.		 ≤ 5
Method b1: At routine test (100% production test) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM, tm = 1 s.		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 3 pF
RIO Insulation resistance, input to output(5) VIO = 500 V, TA = 25°C > 1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 3000 VRMS, t = 60 s (qualification test), VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100% production test) 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the intrinsic surge immunity of the package.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.