JAJSSC7 December   2023 TPSI3100

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Over-current Fault Error
        5. 9.2.2.5 Over-current Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • DVX|16
サーマルパッド・メカニカル・データ
発注情報

Device Operation

VDDP must be supplied independently by a low impedance external supply that can deliver the required power. When VDDP power is present and CE is a logic high, power transfers from the primary side to the secondary side. Setting the EN pin logic high or low asserts or deasserts VDRV, thereby enabling or disabling the external switch, respectively. Figure 8-9 shows the basic set-up required for proper operation which requires EN, VDDP, and VSSP signals. EN may be driven up to 5.5-V which is normally driven from circuitry on the same rail as VDDP. In this example, the TPSI310x is being used to drive back-to-back MOSFETs in a common-source configuration. Driving back-to-back MOSFETs is required for AC switching applications or DC switching where reverse blocking is required. CVDDP provides the required decoupling capacitance for the VDDP supply. CDIV1 and CDIV2 provide the required decoupling capacitance of the VDDH/VDDM supply rails to provide peak current to drive the external MOSFETs.

GUID-20220829-SS0I-XTQT-ZLTS-VB9FJ02XMFCW-low.svg Figure 8-9 Simplified Schematic

Figure 8-10 shows the basic operation from start up to steady state conditions.

  • At T1: VDDP powers up the device. FLTn, ALMn, and PGOOD are asserted low.
  • At T2 and T3: TPSI310x begins to transfer power from VDDP to the secondary side for a fixed burst period (25 μs typical), which begins to charge up the VDDH and VDDM secondary side rails. Power transfer continues as long as VDDP is present (and CE remains high). The time required to fully charge VDDH depends on several factors including the values of VDDP, CDIV1, CDIV2, the amount of auxiliary load drawn from VDDM, and the overall power transfer efficiency.
  • At T4, T5, and T6: After four burst periods, the FLTn, ALMn, and PGOOD are released and begin to reflect their respective status. PGOOD asserts high if VDDM and VDDH are both above their UVLO thresholds, otherwise remains asserted low. FLTn and ALMn indicate the status of their comparator outputs. In this example, since FLTn_CMP and ALMn_CMP are tied to VSSS, FLTn and ALMn assert high. The status indicators are always transferred sequentially in the order of FLTn, ALMn, and PGOOD with a delay of approximately 400 ns between each indicator.
  • At T7 and T8: EN is asserted high and VDRV asserts high. Note that VDRV will not assert high until VDDH and VDDM are both above their UVLO thresholds. Due to latency of the FLTn, ALMn, and PGOOD indicators, it is possible that VDRV asserts high prior to PGOOD asserting high.
GUID-20221115-SS0I-ZDDN-0FXN-ZXVL9LVTCDHP-low.svg Figure 8-10 TPSI310x Typical Start-up (CE = VDDP, FLTn_CMP = 0, ALMn_CMP = 0)

Figure 8-11 shows start up sequence where VDDP, CE, and EN signals are tied together.

  • At T1: VDDP powers up the device. FLTn, ALMn, and PGOOD are asserted low.
  • At T2 and T3: TPSI310x begins to transfer power from VDDP to the secondary side for a fixed burst period (25 μs typical), which begins to charge up the VDDH and VDDM secondary side rails.
  • At T4: VDRV asserts high when both VDDH and VDDM are above their UVLO thresholds.
  • At T5, T6, and T7: After four burst periods, the FLTn, ALMn, and PGOOD are released and begin to reflect their respective status. In this specific example, it is assumed that VDDH and VDDM rails have charged up beyond their UVLO thresholds under the four burst periods (100 μs). In this case, due to the PGOOD latency, PGOOD is asserted high after VDRV is asserted high.
GUID-20231107-SS0I-RZXS-PHHR-T8N7HLQ2ZD3D-low.svg Figure 8-11 TPSI310x Typical Start-up (CE = EN = VDDP, FLTn_CMP = 0, ALMn_CMP = 0)

To reduce average power, the TPSI310x transfers power from the primary side to the secondary side in a burst fashion. The period of the burst is fixed while the burst on time is determined internally by the control loop regulating the VDDM voltage. The burst on time is automatically adjusted based upon the status of the VDDM voltage thereby optimizing power transfer for a given load condition. During power up, the device operates at the highest power setting. This helps to quickly charge up the VDDM and VDDH rails.