JAJSSC7
December 2023
TPSI3100
ADVANCE INFORMATION
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristic Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Transmission of the Enable State
8.3.2
Power Transmission
8.3.3
Gate Driver
8.3.4
Chip Enable (CE)
8.3.5
Comparators
8.3.5.1
Fault Comparator
8.3.5.2
Alarm Comparator
8.3.5.3
Comparator De-glitch
8.3.6
VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
8.3.7
Thermal Shutdown
8.4
Device Operation
8.5
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
CDIV1, CDIV2 Capacitance
9.2.2.2
Start-up Time and Recovery Time
9.2.2.3
RSHUNT, R1, and R2 Selection
9.2.2.4
Over-current Fault Error
9.2.2.5
Over-current Alarm Error
9.2.2.6
VDDP Capacitance, CVDDP
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DVX|16
サーマルパッド・メカニカル・データ
発注情報
jajssc7_oa
7
Parameter Measurement Information
Figure 7-1
VDRV Timing, (CE = 1 or CE = VDDP, FLTn_CMP = ALMn_CMP = 0)
Figure 7-2
VDRV Auto-Recovery Timing (CE = 1 or CE = VDDP)
Figure 7-3
Common-Mode Transient Immunity Test Circuit