JAJSSC7 December   2023 TPSI3100

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Over-current Fault Error
        5. 9.2.2.5 Over-current Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

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発注情報

Fault Comparator

The TPSI310x and TPSI313x devices include one fault comparator that is used to quickly assert the output driver, VDRV, low to allow for the fastest disable time of the external power switch. This is useful for critical events such as over-current protection (OCP) to protect the external power switch and downstream circuitry. The block diagram of the fault comparator is shown in Figure 8-8. The TPSI311x devices have two fault comparators. This can be useful for applications such as bi-directional OCP or whenever there are two independent critical events required to protect the external power switch. The TPSI312x device does not support any fault comparators, only alarm comparators.

GUID-20230104-SS0I-KNTW-ZQNJ-H2XTHRKQDCXT-low.svg Figure 8-6 Fault Comparator Block Diagram

If the input voltage of the fault comparator, FLTn_CMP, exceeds the internal reference voltage, VREF, the comparator output asserts high. The comparator output is filtered and is adjustable via an external 1% resistor, RRESP, connected from RESP to VSSS. The filtering of low-to-high transitions of the comparator output is adjustable by the external resistor. High-to-low transitions of the comparator output are filtered at a fixed setting. Filtering the comparator output allows for flexibility and application tradeoffs to help minimize false trigger events while still providing adequate protection. The filtered comparator output is then fed into the driver logic. If the comparator output low-to-high event passes through the filter, VDRV is immediately asserted low regardless of the state of EN. The TPSI310x, TPSI311x, and TPSI313x fault comparators are not latched. If a fault condition is removed (FLTn_CMP voltage falls below the internal reference voltage and passes through the filter), VDRV is held low until the recovery timer has elapsed. Once the recovery timer has elapsed, VDRV follows the state of EN. If a fault condition occurs before the recovery timer has elapsed, the recovery timer is restarted.

The comparator output information is transferred to the primary side of the device via back-channel communication (BCC) over the isolation barrier. As shown in Figure 8-8, any low-to-high transition of the comparator output (fault event) that passes through the filter is extended to make sure the event is captured by the sample logic. Any high-to-low transition of the comparator output (recovery event) that passes through the filter are not extended. A recovery event can be missed by the sample logic if the event does not last longer than the sample period. Therefore, priority is given to fault events over recovery events. FLTn open-drain output is asserted low upon the fault event. If a recovery event occurs and is captured by the sample logic, FLTn open-drain output is set to high-impedance, but VDRV remains asserted low until the recovery timer elapses.

The TPSI310xL, TPSI311xL, and TPSI313xL devices have latched fault comparators as shown in Figure 8-7. Fault events are latched and held until EN is asserted low. Upon a fault event, VDRV asserts low and is held until EN is asserted low and the recovery timer elapses. FLTn is also asserted low and held until EN is asserted low. If the fault event has recovered, FLTn is asserted high even if the recovery timer has not elapsed.

GUID-20230104-SS0I-QGTS-RCKN-LJZDJCLFKFMC-low.svg Figure 8-7 Latched Fault Comparator Block Diagram